clk: qoriq: add clock configuration for ls1088a soc (e0c888c4) · Commits · 戴 / test

Clock on ls1088a chip takes primary clocking input from the external SYSCLK signal. The SYSCLK input (frequency) is multiplied using multiple phase locked loops (PLL) to create a variety of frequencies which can then be passed to a variety of internal logic, including cores and peripheral IP modules. Signed-off-by:

Tang Yuantian <andy.tang@nxp.com> Signed-off-by:

Stephen Boyd <sboyd@codeaurora.org>

drivers/clk/clk-qoriq.c

+12 −0

Original line number	Diff line number	Diff line
		@@ -536,6 +536,17 @@ static const struct clockgen_chipinfo chipinfo[] = {
		.pll_mask = 0x07,
		.flags = CG_PLL_8BIT,
		},
		{
		.compat = "fsl,ls1088a-clockgen",
		.cmux_groups = {
		&clockgen2_cmux_cga12
		},
		.cmux_to_group = {
		0, 0, -1
		},
		.pll_mask = 0x07,
		.flags = CG_VER3 \| CG_LITTLE_ENDIAN,
		},
		{
		.compat = "fsl,ls1012a-clockgen",
		.cmux_groups = {
		@@ -1398,6 +1409,7 @@ CLK_OF_DECLARE(qoriq_clockgen_ls1012a, "fsl,ls1012a-clockgen", clockgen_init);
		CLK_OF_DECLARE(qoriq_clockgen_ls1021a, "fsl,ls1021a-clockgen", clockgen_init);
		CLK_OF_DECLARE(qoriq_clockgen_ls1043a, "fsl,ls1043a-clockgen", clockgen_init);
		CLK_OF_DECLARE(qoriq_clockgen_ls1046a, "fsl,ls1046a-clockgen", clockgen_init);
		CLK_OF_DECLARE(qoriq_clockgen_ls1088a, "fsl,ls1088a-clockgen", clockgen_init);
		CLK_OF_DECLARE(qoriq_clockgen_ls2080a, "fsl,ls2080a-clockgen", clockgen_init);

		/* Legacy nodes */

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