Commit e09d40bd authored by Christian König's avatar Christian König Committed by Alex Deucher
Browse files

drm/amdgpu: change how we update mmRLC_SPM_MC_CNTL 



In pp_one_vf mode avoid the extra overhead and read/write the
registers without the KIQ.

Signed-off-by: default avatarChristian König <christian.koenig@amd.com>
Reviewed-by: default avatarMonk Liu <monk.liu@amd.com>
Acked-by: default avatarYintian Tao <yintian.tao@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent a891d239

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

+10 −3
Original line number Diff line number Diff line
@@ -7030,13 +7030,20 @@ static int gfx_v10_0_update_gfx_clock_gating(struct amdgpu_device *adev, 


static void gfx_v10_0_update_spm_vmid(struct amdgpu_device *adev, unsigned vmid)

{

	u32 data;

	u32 reg, data;



	data = RREG32_SOC15(GC, 0, mmRLC_SPM_MC_CNTL);

	reg = SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_MC_CNTL);

	if (amdgpu_sriov_is_pp_one_vf(adev))

		data = RREG32_NO_KIQ(reg);

	else

		data = RREG32(reg);



	data &= ~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK;

	data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT;



	if (amdgpu_sriov_is_pp_one_vf(adev))

		WREG32_SOC15_NO_KIQ(GC, 0, mmRLC_SPM_MC_CNTL, data);

	else

		WREG32_SOC15(GC, 0, mmRLC_SPM_MC_CNTL, data);

}

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

+8 −2
Original line number Diff line number Diff line
@@ -5615,11 +5615,17 @@ static void gfx_v8_0_update_spm_vmid(struct amdgpu_device *adev, unsigned vmid) 
{

	u32 data;



	if (amdgpu_sriov_is_pp_one_vf(adev))

		data = RREG32_NO_KIQ(mmRLC_SPM_VMID);

	else

		data = RREG32(mmRLC_SPM_VMID);



	data &= ~RLC_SPM_VMID__RLC_SPM_VMID_MASK;

	data |= (vmid & RLC_SPM_VMID__RLC_SPM_VMID_MASK) << RLC_SPM_VMID__RLC_SPM_VMID__SHIFT;



	if (amdgpu_sriov_is_pp_one_vf(adev))

		WREG32_NO_KIQ(mmRLC_SPM_VMID, data);

	else

		WREG32(mmRLC_SPM_VMID, data);

}

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

+10 −3
Original line number Diff line number Diff line
@@ -4950,13 +4950,20 @@ static int gfx_v9_0_update_gfx_clock_gating(struct amdgpu_device *adev, 


static void gfx_v9_0_update_spm_vmid(struct amdgpu_device *adev, unsigned vmid)

{

	u32 data;

	u32 reg, data;



	data = RREG32_SOC15(GC, 0, mmRLC_SPM_MC_CNTL);

	reg = SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_MC_CNTL);

	if (amdgpu_sriov_is_pp_one_vf(adev))

		data = RREG32_NO_KIQ(reg);

	else

		data = RREG32(reg);



	data &= ~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK;

	data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT;



	if (amdgpu_sriov_is_pp_one_vf(adev))

		WREG32_SOC15_NO_KIQ(GC, 0, mmRLC_SPM_MC_CNTL, data);

	else

		WREG32_SOC15(GC, 0, mmRLC_SPM_MC_CNTL, data);

}

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