Commit e0836e36 authored by Simon Horman's avatar Simon Horman Committed by Geert Uytterhoeven
Browse files

clk: renesas: rcar-gen3: Remove CLK_TYPE_GEN3_Z2 



After recent reworking of Z and Z2 clk handling
CLK_TYPE_GEN3_Z and CLK_TYPE_GEN3_Z2 have come to have precisely
the same meaning. Remove this redundancy by eliminating the latter.

This is not expected to have any run-time effect.

As suggested by Geert Uytterhoeven.

Signed-off-by: default avatarSimon Horman <horms+renesas@verge.net.au>
Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
parent 10d9ea51

drivers/clk/renesas/r8a774a1-cpg-mssr.c

+1 −1
Original line number Diff line number Diff line
@@ -72,7 +72,7 @@ static const struct cpg_core_clk r8a774a1_core_clks[] __initconst = { 


	/* Core Clock Outputs */

	DEF_GEN3_Z("z",		R8A774A1_CLK_Z,     CLK_TYPE_GEN3_Z,  CLK_PLL0, 2, 8),

	DEF_GEN3_Z("z2",	R8A774A1_CLK_Z2,    CLK_TYPE_GEN3_Z2, CLK_PLL2, 2, 0),

	DEF_GEN3_Z("z2",	R8A774A1_CLK_Z2,    CLK_TYPE_GEN3_Z,  CLK_PLL2, 2, 0),

	DEF_FIXED("ztr",        R8A774A1_CLK_ZTR,   CLK_PLL1_DIV2,  6, 1),

	DEF_FIXED("ztrd2",      R8A774A1_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),

	DEF_FIXED("zt",         R8A774A1_CLK_ZT,    CLK_PLL1_DIV2,  4, 1),

drivers/clk/renesas/r8a7795-cpg-mssr.c

+1 −1
Original line number Diff line number Diff line
@@ -75,7 +75,7 @@ static struct cpg_core_clk r8a7795_core_clks[] __initdata = { 


	/* Core Clock Outputs */

	DEF_GEN3_Z("z",         R8A7795_CLK_Z,     CLK_TYPE_GEN3_Z,  CLK_PLL0, 2, 8),

	DEF_GEN3_Z("z2",        R8A7795_CLK_Z2,    CLK_TYPE_GEN3_Z2, CLK_PLL2, 2, 0),

	DEF_GEN3_Z("z2",        R8A7795_CLK_Z2,    CLK_TYPE_GEN3_Z,  CLK_PLL2, 2, 0),

	DEF_FIXED("ztr",        R8A7795_CLK_ZTR,   CLK_PLL1_DIV2,  6, 1),

	DEF_FIXED("ztrd2",      R8A7795_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),

	DEF_FIXED("zt",         R8A7795_CLK_ZT,    CLK_PLL1_DIV2,  4, 1),

drivers/clk/renesas/r8a7796-cpg-mssr.c

+1 −1
Original line number Diff line number Diff line
@@ -75,7 +75,7 @@ static const struct cpg_core_clk r8a7796_core_clks[] __initconst = { 


	/* Core Clock Outputs */

	DEF_GEN3_Z("z",         R8A7796_CLK_Z,     CLK_TYPE_GEN3_Z,  CLK_PLL0, 2, 8),

	DEF_GEN3_Z("z2",        R8A7796_CLK_Z2,    CLK_TYPE_GEN3_Z2, CLK_PLL2, 2, 0),

	DEF_GEN3_Z("z2",        R8A7796_CLK_Z2,    CLK_TYPE_GEN3_Z,  CLK_PLL2, 2, 0),

	DEF_FIXED("ztr",        R8A7796_CLK_ZTR,   CLK_PLL1_DIV2,  6, 1),

	DEF_FIXED("ztrd2",      R8A7796_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),

	DEF_FIXED("zt",         R8A7796_CLK_ZT,    CLK_PLL1_DIV2,  4, 1),

drivers/clk/renesas/rcar-gen3-cpg.c

+0 −1
Original line number Diff line number Diff line
@@ -659,7 +659,6 @@ struct clk * __init rcar_gen3_cpg_clk_register(struct device *dev, 
		break;



	case CLK_TYPE_GEN3_Z:

	case CLK_TYPE_GEN3_Z2:

		return cpg_z_clk_register(core->name, __clk_get_name(parent),

					  base, core->div, core->offset);

drivers/clk/renesas/rcar-gen3-cpg.h

+0 −1
Original line number Diff line number Diff line
@@ -21,7 +21,6 @@ enum rcar_gen3_clk_types { 
	CLK_TYPE_GEN3_R,

	CLK_TYPE_GEN3_MDSEL,	/* Select parent/divider using mode pin */

	CLK_TYPE_GEN3_Z,

	CLK_TYPE_GEN3_Z2,

	CLK_TYPE_GEN3_OSC,	/* OSC EXTAL predivider and fixed divider */

	CLK_TYPE_GEN3_RCKSEL,	/* Select parent/divider using RCKCR.CKSEL */

	CLK_TYPE_GEN3_RPCSRC,

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