Commit e07f8354 authored by Taniya Das's avatar Taniya Das Committed by Bjorn Andersson
Browse files

arm64: dts: sc7180: Add clock controller nodes 



Add the display, video & graphics clock controller nodes supported on
SC7180.

NOTE: the dispcc needs input clocks from various PHYs that aren't in
the device tree yet.  For now we'll leave these stubbed out with <0>,
which is apparently the magic way to do this.  These clocks aren't
really "optional" and this stubbing out method is apparently the best
way to handle it.

Signed-off-by: default avatarTaniya Das <tdas@codeaurora.org>
Signed-off-by: default avatarDouglas Anderson <dianders@chromium.org>
Link: https://lore.kernel.org/r/20200203103049.v4.15.I1a4b93fb005791e29a9dcf288fc8bd459a555a59@changeid


Signed-off-by: default avatarBjorn Andersson <bjorn.andersson@linaro.org>
parent af85ef13

arch/arm64/boot/dts/qcom/sc7180.dtsi

+47 −0
Original line number Diff line number Diff line
@@ -5,8 +5,11 @@ 
 * Copyright (c) 2019, The Linux Foundation. All rights reserved.

 */



#include <dt-bindings/clock/qcom,dispcc-sc7180.h>

#include <dt-bindings/clock/qcom,gcc-sc7180.h>

#include <dt-bindings/clock/qcom,gpucc-sc7180.h>

#include <dt-bindings/clock/qcom,rpmh.h>

#include <dt-bindings/clock/qcom,videocc-sc7180.h>

#include <dt-bindings/interrupt-controller/arm-gic.h>

#include <dt-bindings/phy/phy-qcom-qusb2.h>

#include <dt-bindings/power/qcom-aoss-qmp.h>
@@ -1190,6 +1193,20 @@ 
			status = "disabled";

		};



		gpucc: clock-controller@5090000 {

			compatible = "qcom,sc7180-gpucc";

			reg = <0 0x05090000 0 0x9000>;

			clocks = <&rpmhcc RPMH_CXO_CLK>,

				 <&gcc GCC_GPU_GPLL0_CLK_SRC>,

				 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;

			clock-names = "bi_tcxo",

				      "gcc_gpu_gpll0_clk_src",

				      "gcc_gpu_gpll0_div_clk_src";

			#clock-cells = <1>;

			#reset-cells = <1>;

			#power-domain-cells = <1>;

		};



		qspi: spi@88dc000 {

			compatible = "qcom,qspi-v1";

			reg = <0 0x088dc000 0 0x600>;
@@ -1302,6 +1319,36 @@ 
			};

		};



		videocc: clock-controller@ab00000 {

			compatible = "qcom,sc7180-videocc";

			reg = <0 0x0ab00000 0 0x10000>;

			clocks = <&rpmhcc RPMH_CXO_CLK>;

			clock-names = "bi_tcxo";

			#clock-cells = <1>;

			#reset-cells = <1>;

			#power-domain-cells = <1>;

		};



		dispcc: clock-controller@af00000 {

			compatible = "qcom,sc7180-dispcc";

			reg = <0 0x0af00000 0 0x200000>;

			clocks = <&rpmhcc RPMH_CXO_CLK>,

				 <&gcc GCC_DISP_GPLL0_CLK_SRC>,

				 <0>,

				 <0>,

				 <0>,

				 <0>;

			clock-names = "bi_tcxo",

				      "gcc_disp_gpll0_clk_src",

				      "dsi0_phy_pll_out_byteclk",

				      "dsi0_phy_pll_out_dsiclk",

				      "dp_phy_pll_link_clk",

				      "dp_phy_pll_vco_div_clk";

			#clock-cells = <1>;

			#reset-cells = <1>;

			#power-domain-cells = <1>;

		};



		pdc: interrupt-controller@b220000 {

			compatible = "qcom,sc7180-pdc", "qcom,pdc";

			reg = <0 0x0b220000 0 0x30000>;

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