Commit e0600a94 authored by Joseph Gravenor's avatar Joseph Gravenor Committed by Alex Deucher
Browse files

drm/amd/display: update sr latency for renoir when using lpddr4 



[Why]
DF team has produced more optimized sr latency numbers, for lpddr4

[How]
change the sr laency in the lpddr4 wm table to the new latency
number

Signed-off-by: default avatarJoseph Gravenor <joseph.gravenor@amd.com>
Reviewed-by: default avatarTony Cheng <Tony.Cheng@amd.com>
Acked-by: default avatarLeo Li <sunpeng.li@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 2f39835c

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c

+8 −8
Original line number Diff line number Diff line
@@ -563,32 +563,32 @@ struct wm_table lpddr4_wm_table = { 
			.wm_inst = WM_A,

			.wm_type = WM_TYPE_PSTATE_CHG,

			.pstate_latency_us = 11.65333,

			.sr_exit_time_us = 12.5,

			.sr_enter_plus_exit_time_us = 17.0,

			.sr_exit_time_us = 5.32,

			.sr_enter_plus_exit_time_us = 6.38,

			.valid = true,

		},

		{

			.wm_inst = WM_B,

			.wm_type = WM_TYPE_PSTATE_CHG,

			.pstate_latency_us = 11.65333,

			.sr_exit_time_us = 12.5,

			.sr_enter_plus_exit_time_us = 17.0,

			.sr_exit_time_us = 9.82,

			.sr_enter_plus_exit_time_us = 11.196,

			.valid = true,

		},

		{

			.wm_inst = WM_C,

			.wm_type = WM_TYPE_PSTATE_CHG,

			.pstate_latency_us = 11.65333,

			.sr_exit_time_us = 12.5,

			.sr_enter_plus_exit_time_us = 17.0,

			.sr_exit_time_us = 9.89,

			.sr_enter_plus_exit_time_us = 11.24,

			.valid = true,

		},

		{

			.wm_inst = WM_D,

			.wm_type = WM_TYPE_PSTATE_CHG,

			.pstate_latency_us = 11.65333,

			.sr_exit_time_us = 12.5,

			.sr_enter_plus_exit_time_us = 17.0,

			.sr_exit_time_us = 9.748,

			.sr_enter_plus_exit_time_us = 11.102,

			.valid = true,

		},

	}

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