Commit e0457659 authored by Dmytro Laktyushkin's avatar Dmytro Laktyushkin Committed by Alex Deucher
Browse files

drm/amd/display: allow 18 bit dp output on DCN3 



We need this to pass dp compliance.

Signed-off-by: default avatarDmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: default avatarChris Park <Chris.Park@amd.com>
Reviewed-by: default avatarNikola Cornij <nikola.cornij@amd.com>
Acked-by: default avatarRodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent d95c368a

drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c

+0 −14
Original line number Diff line number Diff line
@@ -2020,20 +2020,6 @@ static bool dcn30_internal_validate_bw( 


	dml_log_mode_support_params(&context->bw_ctx.dml);



	/* TODO: Need to check calculated vlevel why that fails validation of below resolutions */

	if (context->res_ctx.pipe_ctx[0].stream != NULL) {

		if (context->res_ctx.pipe_ctx[0].stream->timing.h_addressable == 640  && context->res_ctx.pipe_ctx[0].stream->timing.v_addressable == 480)

			vlevel = 0;

		if (context->res_ctx.pipe_ctx[0].stream->timing.h_addressable == 1280 && context->res_ctx.pipe_ctx[0].stream->timing.v_addressable == 800)

			vlevel = 0;

		if (context->res_ctx.pipe_ctx[0].stream->timing.h_addressable == 1280 && context->res_ctx.pipe_ctx[0].stream->timing.v_addressable == 768)

			vlevel = 0;

		if (context->res_ctx.pipe_ctx[0].stream->timing.h_addressable == 1280 && context->res_ctx.pipe_ctx[0].stream->timing.v_addressable == 1024)

			vlevel = 0;

		if (context->res_ctx.pipe_ctx[0].stream->timing.h_addressable == 2048 && context->res_ctx.pipe_ctx[0].stream->timing.v_addressable == 1536)

			vlevel = 0;

	}



	if (vlevel == context->bw_ctx.dml.soc.num_states)

		goto validate_fail;

drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c

+1 −1
Original line number Diff line number Diff line
@@ -3628,7 +3628,7 @@ static double TruncToValidBPP( 
			}

		}

	} else {

		if (!((DSCEnable == false && (DesiredBPP == NonDSCBPP2 || DesiredBPP == NonDSCBPP1 || DesiredBPP == NonDSCBPP0)) ||

		if (!((DSCEnable == false && (DesiredBPP == NonDSCBPP2 || DesiredBPP == NonDSCBPP1 || DesiredBPP == NonDSCBPP0 || DesiredBPP == 18)) ||

				(DSCEnable && DesiredBPP >= MinDSCBPP && DesiredBPP <= MaxDSCBPP))) {

			return BPP_INVALID;

		} else {

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