drm/amdgpu: Hardcode reg access using L1 security (e0301317) · Commits · 戴 / test

Under Vega10 SR-IOV VF, L1 register access mode should be enabled by default as the non-security VF will no longer be supported. Signed-off-by:

drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c

+6 −9

Original line number	Diff line number	Diff line
		@@ -451,18 +451,15 @@ void xgpu_ai_mailbox_put_irq(struct amdgpu_device *adev)

		static void xgpu_ai_init_reg_access_mode(struct amdgpu_device *adev)
		{
		uint32_t rlc_fw_ver = RREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_6);
		uint32_t sos_fw_ver = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_58);

		adev->virt.reg_access_mode = AMDGPU_VIRT_REG_ACCESS_LEGACY;

		if (rlc_fw_ver >= 0x5d)
		/* Enable L1 security reg access mode by defaul, as non-security VF
		* will no longer be supported.
		*/
		adev->virt.reg_access_mode \|= AMDGPU_VIRT_REG_ACCESS_RLC;

		if (sos_fw_ver >= 0x80455)
		adev->virt.reg_access_mode \|= AMDGPU_VIRT_REG_ACCESS_PSP_PRG_IH;

		if (sos_fw_ver >= 0x8045b)
		adev->virt.reg_access_mode \|= AMDGPU_VIRT_REG_SKIP_SEETING;
		}