Commit e0291f1d authored by Christophe Leroy's avatar Christophe Leroy Committed by Michael Ellerman
Browse files

powerpc/32: drop CPU_FTR_UNIFIED_ID_CACHE 



Only 601 and e200 have unified I/D cache.

Drop the feature and use CONFIG_PPC_BOOK3S_601 and CONFIG_E200.

Signed-off-by: default avatarChristophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: default avatarMichael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/b5902144266d2f4eed1ffea53915bd0245841e02.1566834712.git.christophe.leroy@c-s.fr
parent 39097b9c

arch/powerpc/include/asm/cputable.h

+2 −3
Original line number Diff line number Diff line
@@ -158,7 +158,6 @@ static inline void cpu_feature_keys_init(void) { } 
#define CPU_FTR_NEED_COHERENT		ASM_CONST(0x01000000)

#define CPU_FTR_NO_BTIC			ASM_CONST(0x02000000)

#define CPU_FTR_PPC_LE			ASM_CONST(0x04000000)

#define CPU_FTR_UNIFIED_ID_CACHE	ASM_CONST(0x08000000)

#define CPU_FTR_SPE			ASM_CONST(0x10000000)

#define CPU_FTR_NEED_PAIRED_STWCX	ASM_CONST(0x20000000)

#define CPU_FTR_INDEXED_DCR		ASM_CONST(0x40000000)
@@ -292,7 +291,7 @@ static inline void cpu_feature_keys_init(void) { } 
#endif



#define CPU_FTRS_PPC601	(CPU_FTR_COMMON | \

	CPU_FTR_COHERENT_ICACHE | CPU_FTR_UNIFIED_ID_CACHE)

	CPU_FTR_COHERENT_ICACHE)

#define CPU_FTRS_603	(CPU_FTR_COMMON | CPU_FTR_MAYBE_CAN_DOZE | \

	    CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE | CPU_FTR_NOEXECUTE)

#define CPU_FTRS_604	(CPU_FTR_COMMON | CPU_FTR_PPC_LE)
@@ -383,7 +382,7 @@ static inline void cpu_feature_keys_init(void) { } 
#define CPU_FTRS_47X	(CPU_FTRS_440x6)

#define CPU_FTRS_E200	(CPU_FTR_SPE_COMP | \

	    CPU_FTR_NODSISRALIGN | CPU_FTR_COHERENT_ICACHE | \

	    CPU_FTR_UNIFIED_ID_CACHE | CPU_FTR_NOEXECUTE | \

	    CPU_FTR_NOEXECUTE | \

	    CPU_FTR_DEBUG_LVL_EXC)

#define CPU_FTRS_E500	(CPU_FTR_MAYBE_CAN_DOZE | \

	    CPU_FTR_SPE_COMP | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_NODSISRALIGN | \

arch/powerpc/kernel/misc_32.S

+2 −2
Original line number Diff line number Diff line
@@ -292,14 +292,14 @@ _GLOBAL(flush_instruction_cache) 
	iccci	0,r3

#endif

#elif defined(CONFIG_FSL_BOOKE)

BEGIN_FTR_SECTION

#ifdef CONFIG_E200

	mfspr   r3,SPRN_L1CSR0

	ori     r3,r3,L1CSR0_CFI|L1CSR0_CLFC

	/* msync; isync recommended here */

	mtspr   SPRN_L1CSR0,r3

	isync

	blr

END_FTR_SECTION_IFSET(CPU_FTR_UNIFIED_ID_CACHE)

#endif

	mfspr	r3,SPRN_L1CSR1

	ori	r3,r3,L1CSR1_ICFI|L1CSR1_ICLFR

	mtspr	SPRN_L1CSR1,r3

arch/powerpc/kernel/setup_32.c

+1 −1
Original line number Diff line number Diff line
@@ -206,6 +206,6 @@ __init void initialize_cache_info(void) 
	dcache_bsize = cur_cpu_spec->dcache_bsize;

	icache_bsize = cur_cpu_spec->icache_bsize;

	ucache_bsize = 0;

	if (cpu_has_feature(CPU_FTR_UNIFIED_ID_CACHE))

	if (IS_ENABLED(CONFIG_PPC_BOOK3S_601) || IS_ENABLED(CONFIG_E200))

		ucache_bsize = icache_bsize = dcache_bsize;

}

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