Commit dfe9cfcc authored by Laurent Pinchart's avatar Laurent Pinchart Committed by Tomi Valkeinen
Browse files

drm: omapdrm: Use kernel integer types 



The standard kernel integer types are [us]{8,16,32}. Use them instead of
the u?int{8,16,32}_t types.

Signed-off-by: default avatarLaurent Pinchart <laurent.pinchart@ideasonboard.com>
Reviewed-by: default avatarSebastian Reichel <sebastian.reichel@collabora.co.uk>
Signed-off-by: default avatarTomi Valkeinen <tomi.valkeinen@ti.com>
parent f073d78e

drivers/gpu/drm/omapdrm/omap_crtc.c

+6 −6
Original line number Diff line number Diff line
@@ -272,7 +272,7 @@ static const struct dss_mgr_ops mgr_ops = { 
 * Setup, Flush and Page Flip

 */



void omap_crtc_error_irq(struct drm_crtc *crtc, uint32_t irqstatus)

void omap_crtc_error_irq(struct drm_crtc *crtc, u32 irqstatus)

{

	struct omap_crtc *omap_crtc = to_omap_crtc(crtc);
@@ -492,7 +492,7 @@ static int omap_crtc_atomic_check(struct drm_crtc *crtc, 
	struct drm_plane_state *pri_state;



	if (state->color_mgmt_changed && state->gamma_lut) {

		uint length = state->gamma_lut->length /

		unsigned int length = state->gamma_lut->length /

			sizeof(struct drm_color_lut);



		if (length < 2)
@@ -526,7 +526,7 @@ static void omap_crtc_atomic_flush(struct drm_crtc *crtc, 


	if (crtc->state->color_mgmt_changed) {

		struct drm_color_lut *lut = NULL;

		uint length = 0;

		unsigned int length = 0;



		if (crtc->state->gamma_lut) {

			lut = (struct drm_color_lut *)
@@ -557,7 +557,7 @@ static void omap_crtc_atomic_flush(struct drm_crtc *crtc, 
static int omap_crtc_atomic_set_property(struct drm_crtc *crtc,

					 struct drm_crtc_state *state,

					 struct drm_property *property,

					 uint64_t val)

					 u64 val)

{

	struct omap_drm_private *priv = crtc->dev->dev_private;

	struct drm_plane_state *plane_state;
@@ -585,7 +585,7 @@ static int omap_crtc_atomic_set_property(struct drm_crtc *crtc, 
static int omap_crtc_atomic_get_property(struct drm_crtc *crtc,

					 const struct drm_crtc_state *state,

					 struct drm_property *property,

					 uint64_t *val)

					 u64 *val)

{

	struct omap_drm_private *priv = crtc->dev->dev_private;

	struct omap_crtc_state *omap_state = to_omap_crtc_state(state);
@@ -732,7 +732,7 @@ struct drm_crtc *omap_crtc_init(struct drm_device *dev, 
	 * gamma table is not supprted.

	 */

	if (priv->dispc_ops->mgr_gamma_size(channel)) {

		uint gamma_lut_size = 256;

		unsigned int gamma_lut_size = 256;



		drm_crtc_enable_color_mgmt(crtc, 0, false, gamma_lut_size);

		drm_mode_crtc_set_gamma_size(crtc, gamma_lut_size);

drivers/gpu/drm/omapdrm/omap_crtc.h

+1 −1
Original line number Diff line number Diff line
@@ -37,7 +37,7 @@ void omap_crtc_pre_uninit(void); 
struct drm_crtc *omap_crtc_init(struct drm_device *dev,

		struct drm_plane *plane, struct omap_dss_device *dssdev);

int omap_crtc_wait_pending(struct drm_crtc *crtc);

void omap_crtc_error_irq(struct drm_crtc *crtc, uint32_t irqstatus);

void omap_crtc_error_irq(struct drm_crtc *crtc, u32 irqstatus);

void omap_crtc_vblank_irq(struct drm_crtc *crtc);



#endif /* __OMAPDRM_CRTC_H__ */

drivers/gpu/drm/omapdrm/omap_dmm_priv.h

+5 −5
Original line number Diff line number Diff line
@@ -102,10 +102,10 @@ struct pat_ctrl { 
};



struct pat {

	uint32_t next_pa;

	u32 next_pa;

	struct pat_area area;

	struct pat_ctrl ctrl;

	uint32_t data_pa;

	u32 data_pa;

};



#define DMM_FIXED_RETRY_COUNT 1000
@@ -129,7 +129,7 @@ struct dmm_txn { 
	void *engine_handle;

	struct tcm *tcm;



	uint8_t *current_va;

	u8 *current_va;

	dma_addr_t current_pa;



	struct pat *last_pat;
@@ -140,7 +140,7 @@ struct refill_engine { 
	struct dmm *dmm;

	struct tcm *tcm;



	uint8_t *refill_va;

	u8 *refill_va;

	dma_addr_t refill_pa;



	/* only one trans per engine for now */
@@ -154,7 +154,7 @@ struct refill_engine { 
};



struct dmm_platform_data {

	uint32_t cpu_cache_flags;

	u32 cpu_cache_flags;

};



struct dmm {

drivers/gpu/drm/omapdrm/omap_dmm_tiler.c

+23 −23
Original line number Diff line number Diff line
@@ -58,11 +58,11 @@ static DEFINE_SPINLOCK(list_lock); 
	}



static const struct {

	uint32_t x_shft;	/* unused X-bits (as part of bpp) */

	uint32_t y_shft;	/* unused Y-bits (as part of bpp) */

	uint32_t cpp;		/* bytes/chars per pixel */

	uint32_t slot_w;	/* width of each slot (in pixels) */

	uint32_t slot_h;	/* height of each slot (in pixels) */

	u32 x_shft;	/* unused X-bits (as part of bpp) */

	u32 y_shft;	/* unused Y-bits (as part of bpp) */

	u32 cpp;		/* bytes/chars per pixel */

	u32 slot_w;	/* width of each slot (in pixels) */

	u32 slot_h;	/* height of each slot (in pixels) */

} geom[TILFMT_NFORMATS] = {

	[TILFMT_8BIT]  = GEOM(0, 0, 1),

	[TILFMT_16BIT] = GEOM(0, 1, 2),
@@ -72,7 +72,7 @@ static const struct { 




/* lookup table for registers w/ per-engine instances */

static const uint32_t reg[][4] = {

static const u32 reg[][4] = {

	[PAT_STATUS] = {DMM_PAT_STATUS__0, DMM_PAT_STATUS__1,

			DMM_PAT_STATUS__2, DMM_PAT_STATUS__3},

	[PAT_DESCR]  = {DMM_PAT_DESCR__0, DMM_PAT_DESCR__1,
@@ -111,10 +111,10 @@ static void *alloc_dma(struct dmm_txn *txn, size_t sz, dma_addr_t *pa) 
}



/* check status and spin until wait_mask comes true */

static int wait_status(struct refill_engine *engine, uint32_t wait_mask)

static int wait_status(struct refill_engine *engine, u32 wait_mask)

{

	struct dmm *dmm = engine->dmm;

	uint32_t r = 0, err, i;

	u32 r = 0, err, i;



	i = DMM_FIXED_RETRY_COUNT;

	while (true) {
@@ -158,7 +158,7 @@ static void release_engine(struct refill_engine *engine) 
static irqreturn_t omap_dmm_irq_handler(int irq, void *arg)

{

	struct dmm *dmm = arg;

	uint32_t status = dmm_read(dmm, DMM_PAT_IRQSTATUS);

	u32 status = dmm_read(dmm, DMM_PAT_IRQSTATUS);

	int i;



	/* ack IRQ */
@@ -226,10 +226,10 @@ static struct dmm_txn *dmm_txn_init(struct dmm *dmm, struct tcm *tcm) 
 * corresponding slot is cleared (ie. dummy_pa is programmed)

 */

static void dmm_txn_append(struct dmm_txn *txn, struct pat_area *area,

		struct page **pages, uint32_t npages, uint32_t roll)

		struct page **pages, u32 npages, u32 roll)

{

	dma_addr_t pat_pa = 0, data_pa = 0;

	uint32_t *data;

	u32 *data;

	struct pat *pat;

	struct refill_engine *engine = txn->engine_handle;

	int columns = (1 + area->x1 - area->x0);
@@ -239,7 +239,7 @@ static void dmm_txn_append(struct dmm_txn *txn, struct pat_area *area, 
	pat = alloc_dma(txn, sizeof(*pat), &pat_pa);



	if (txn->last_pat)

		txn->last_pat->next_pa = (uint32_t)pat_pa;

		txn->last_pat->next_pa = (u32)pat_pa;



	pat->area = *area;
@@ -330,7 +330,7 @@ cleanup: 
 * DMM programming

 */

static int fill(struct tcm_area *area, struct page **pages,

		uint32_t npages, uint32_t roll, bool wait)

		u32 npages, u32 roll, bool wait)

{

	int ret = 0;

	struct tcm_area slice, area_s;
@@ -378,7 +378,7 @@ static int fill(struct tcm_area *area, struct page **pages, 
/* note: slots for which pages[i] == NULL are filled w/ dummy page

 */

int tiler_pin(struct tiler_block *block, struct page **pages,

		uint32_t npages, uint32_t roll, bool wait)

		u32 npages, u32 roll, bool wait)

{

	int ret;
@@ -398,8 +398,8 @@ int tiler_unpin(struct tiler_block *block) 
/*

 * Reserve/release

 */

struct tiler_block *tiler_reserve_2d(enum tiler_fmt fmt, uint16_t w,

		uint16_t h, uint16_t align)

struct tiler_block *tiler_reserve_2d(enum tiler_fmt fmt, u16 w,

		u16 h, u16 align)

{

	struct tiler_block *block = kzalloc(sizeof(*block), GFP_KERNEL);

	u32 min_align = 128;
@@ -542,8 +542,8 @@ dma_addr_t tiler_ssptr(struct tiler_block *block) 
			block->area.p0.y * geom[block->fmt].slot_h);

}



dma_addr_t tiler_tsptr(struct tiler_block *block, uint32_t orient,

		uint32_t x, uint32_t y)

dma_addr_t tiler_tsptr(struct tiler_block *block, u32 orient,

		u32 x, u32 y)

{

	struct tcm_pt *p = &block->area.p0;

	BUG_ON(!validfmt(block->fmt));
@@ -553,14 +553,14 @@ dma_addr_t tiler_tsptr(struct tiler_block *block, uint32_t orient, 
			(p->y * geom[block->fmt].slot_h) + y);

}



void tiler_align(enum tiler_fmt fmt, uint16_t *w, uint16_t *h)

void tiler_align(enum tiler_fmt fmt, u16 *w, u16 *h)

{

	BUG_ON(!validfmt(fmt));

	*w = round_up(*w, geom[fmt].slot_w);

	*h = round_up(*h, geom[fmt].slot_h);

}



uint32_t tiler_stride(enum tiler_fmt fmt, uint32_t orient)

u32 tiler_stride(enum tiler_fmt fmt, u32 orient)

{

	BUG_ON(!validfmt(fmt));
@@ -570,19 +570,19 @@ uint32_t tiler_stride(enum tiler_fmt fmt, uint32_t orient) 
		return 1 << (CONT_WIDTH_BITS + geom[fmt].y_shft);

}



size_t tiler_size(enum tiler_fmt fmt, uint16_t w, uint16_t h)

size_t tiler_size(enum tiler_fmt fmt, u16 w, u16 h)

{

	tiler_align(fmt, &w, &h);

	return geom[fmt].cpp * w * h;

}



size_t tiler_vsize(enum tiler_fmt fmt, uint16_t w, uint16_t h)

size_t tiler_vsize(enum tiler_fmt fmt, u16 w, u16 h)

{

	BUG_ON(!validfmt(fmt));

	return round_up(geom[fmt].cpp * w, PAGE_SIZE) * h;

}



uint32_t tiler_get_cpu_cache_flags(void)

u32 tiler_get_cpu_cache_flags(void)

{

	return omap_dmm->plat_data->cpu_cache_flags;

}

drivers/gpu/drm/omapdrm/omap_dmm_tiler.h

+11 −11
Original line number Diff line number Diff line
@@ -88,30 +88,30 @@ int tiler_map_show(struct seq_file *s, void *arg); 


/* pin/unpin */

int tiler_pin(struct tiler_block *block, struct page **pages,

		uint32_t npages, uint32_t roll, bool wait);

		u32 npages, u32 roll, bool wait);

int tiler_unpin(struct tiler_block *block);



/* reserve/release */

struct tiler_block *tiler_reserve_2d(enum tiler_fmt fmt, uint16_t w, uint16_t h,

				uint16_t align);

struct tiler_block *tiler_reserve_2d(enum tiler_fmt fmt, u16 w, u16 h,

				u16 align);

struct tiler_block *tiler_reserve_1d(size_t size);

int tiler_release(struct tiler_block *block);



/* utilities */

dma_addr_t tiler_ssptr(struct tiler_block *block);

dma_addr_t tiler_tsptr(struct tiler_block *block, uint32_t orient,

		uint32_t x, uint32_t y);

uint32_t tiler_stride(enum tiler_fmt fmt, uint32_t orient);

size_t tiler_size(enum tiler_fmt fmt, uint16_t w, uint16_t h);

size_t tiler_vsize(enum tiler_fmt fmt, uint16_t w, uint16_t h);

void tiler_align(enum tiler_fmt fmt, uint16_t *w, uint16_t *h);

uint32_t tiler_get_cpu_cache_flags(void);

dma_addr_t tiler_tsptr(struct tiler_block *block, u32 orient,

		u32 x, u32 y);

u32 tiler_stride(enum tiler_fmt fmt, u32 orient);

size_t tiler_size(enum tiler_fmt fmt, u16 w, u16 h);

size_t tiler_vsize(enum tiler_fmt fmt, u16 w, u16 h);

void tiler_align(enum tiler_fmt fmt, u16 *w, u16 *h);

u32 tiler_get_cpu_cache_flags(void);

bool dmm_is_available(void);



extern struct platform_driver omap_dmm_driver;



/* GEM bo flags -> tiler fmt */

static inline enum tiler_fmt gem2fmt(uint32_t flags)

static inline enum tiler_fmt gem2fmt(u32 flags)

{

	switch (flags & OMAP_BO_TILED) {

	case OMAP_BO_TILED_8:

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