Commit dfadd9ed authored by Yinghai Lu's avatar Yinghai Lu Committed by Jesse Barnes
Browse files

PCI/x86: detect host bridge config space size w/o using quirks 



Many host bridges support a 4k config space, so check them directy
instead of using quirks to add them.

We only need to do this extra check for host bridges at this point,
because only host bridges are known to have extended address space
without also having a PCI-X/PCI-E caps.  Other devices with this
property could be done with quirks (if there are any).

As a bonus, we can remove the quirks for AMD host bridges with family
10h and 11h since they're not needed any more.

With this patch, we can get correct pci cfg size of new Intel CPUs/IOHs
with host bridges.

Signed-off-by: default avatarYinghai Lu <yinghai@kernel.org>
Acked-by: default avatarH. Peter Anvin <hpa@zytor.com>
Reviewed-by: default avatarMatthew Wilcox <willy@linux.intel.com>
Cc: <stable@kernel.org>
Signed-off-by: default avatarJesse Barnes <jbarnes@virtuousgeek.org>
parent 745be2e7

arch/x86/pci/fixup.c

+0 −20
Original line number Diff line number Diff line
@@ -494,26 +494,6 @@ static void __devinit pci_siemens_interrupt_controller(struct pci_dev *dev) 
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SIEMENS, 0x0015,

			  pci_siemens_interrupt_controller);



/*

 * Regular PCI devices have 256 bytes, but AMD Family 10h/11h CPUs have

 * 4096 bytes configuration space for each function of their processor

 * configuration space.

 */

static void amd_cpu_pci_cfg_space_size(struct pci_dev *dev)

{

	dev->cfg_size = pci_cfg_space_size_ext(dev);

}

DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x1200, amd_cpu_pci_cfg_space_size);

DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x1201, amd_cpu_pci_cfg_space_size);

DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x1202, amd_cpu_pci_cfg_space_size);

DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x1203, amd_cpu_pci_cfg_space_size);

DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x1204, amd_cpu_pci_cfg_space_size);

DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x1300, amd_cpu_pci_cfg_space_size);

DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x1301, amd_cpu_pci_cfg_space_size);

DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x1302, amd_cpu_pci_cfg_space_size);

DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x1303, amd_cpu_pci_cfg_space_size);

DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x1304, amd_cpu_pci_cfg_space_size);



/*

 * SB600: Disable BAR1 on device 14.0 to avoid HPET resources from

 * confusing the PCI engine:

drivers/pci/probe.c

+8 −1
Original line number Diff line number Diff line
@@ -847,6 +847,11 @@ int pci_cfg_space_size(struct pci_dev *dev) 
{

	int pos;

	u32 status;

	u16 class;



	class = dev->class >> 8;

	if (class == PCI_CLASS_BRIDGE_HOST)

		return pci_cfg_space_size_ext(dev);



	pos = pci_find_capability(dev, PCI_CAP_ID_EXP);

	if (!pos) {
@@ -936,7 +941,6 @@ static struct pci_dev *pci_scan_device(struct pci_bus *bus, int devfn) 
	dev->multifunction = !!(hdr_type & 0x80);

	dev->vendor = l & 0xffff;

	dev->device = (l >> 16) & 0xffff;

	dev->cfg_size = pci_cfg_space_size(dev);

	dev->error_state = pci_channel_io_normal;

	set_pcie_port_type(dev);
@@ -952,6 +956,9 @@ static struct pci_dev *pci_scan_device(struct pci_bus *bus, int devfn) 
		return NULL;

	}



	/* need to have dev->class ready */

	dev->cfg_size = pci_cfg_space_size(dev);



	return dev;

}

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