Commit df9828aa authored by Yoshihiro Shimoda's avatar Yoshihiro Shimoda Committed by Joerg Roedel
Browse files

iommu/ipmmu-vmsa: tidyup register definitions 



To support different registers memory mapping hardware easily
in the future, this patch tidies up the register definitions
as below:
 - Add comments to state to which SoCs or SoC families they apply
 - Add categories about MMU "context" and uTLB registers

No change behavior.

Signed-off-by: default avatarYoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Reviewed-by: default avatarNiklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Signed-off-by: default avatarJoerg Roedel <jroedel@suse.de>
parent 77cf9838

drivers/iommu/ipmmu-vmsa.c

+30 −28
Original line number Diff line number Diff line
@@ -101,47 +101,49 @@ static struct ipmmu_vmsa_device *to_ipmmu(struct device *dev) 


#define IM_CTX_SIZE			0x40



#define IMCTR				0x0000

#define IMCTR_INTEN			(1 << 2)

#define IMCTR_FLUSH			(1 << 1)

#define IMCTR_MMUEN			(1 << 0)



#define IMTTBCR				0x0008

#define IMTTBCR_EAE			(1 << 31)

/* MMU "context" registers */

#define IMCTR				0x0000		/* R-Car Gen2/3 */

#define IMCTR_INTEN			(1 << 2)	/* R-Car Gen2/3 */

#define IMCTR_FLUSH			(1 << 1)	/* R-Car Gen2/3 */

#define IMCTR_MMUEN			(1 << 0)	/* R-Car Gen2/3 */



#define IMTTBCR				0x0008		/* R-Car Gen2/3 */

#define IMTTBCR_EAE			(1 << 31)	/* R-Car Gen2/3 */

#define IMTTBCR_SH0_INNER_SHAREABLE	(3 << 12)	/* R-Car Gen2 only */

#define IMTTBCR_ORGN0_WB_WA		(1 << 10)	/* R-Car Gen2 only */

#define IMTTBCR_IRGN0_WB_WA		(1 << 8)	/* R-Car Gen2 only */

#define IMTTBCR_SL0_TWOBIT_LVL_1	(2 << 6)	/* R-Car Gen3 only */

#define IMTTBCR_SL0_LVL_1		(1 << 4)

#define IMTTBCR_SL0_LVL_1		(1 << 4)	/* R-Car Gen2 only */



#define IMBUSCR				0x000c

#define IMBUSCR_DVM			(1 << 2)

#define IMBUSCR_BUSSEL_MASK		(3 << 0)

#define IMBUSCR				0x000c		/* R-Car Gen2 only */

#define IMBUSCR_DVM			(1 << 2)	/* R-Car Gen2 only */

#define IMBUSCR_BUSSEL_MASK		(3 << 0)	/* R-Car Gen2 only */



#define IMTTLBR0			0x0010

#define IMTTUBR0			0x0014

#define IMTTLBR0			0x0010		/* R-Car Gen2/3 */

#define IMTTUBR0			0x0014		/* R-Car Gen2/3 */



#define IMSTR				0x0020

#define IMSTR_MHIT			(1 << 4)

#define IMSTR_ABORT			(1 << 2)

#define IMSTR_PF			(1 << 1)

#define IMSTR_TF			(1 << 0)

#define IMSTR				0x0020		/* R-Car Gen2/3 */

#define IMSTR_MHIT			(1 << 4)	/* R-Car Gen2/3 */

#define IMSTR_ABORT			(1 << 2)	/* R-Car Gen2/3 */

#define IMSTR_PF			(1 << 1)	/* R-Car Gen2/3 */

#define IMSTR_TF			(1 << 0)	/* R-Car Gen2/3 */



#define IMMAIR0				0x0028

#define IMMAIR0				0x0028		/* R-Car Gen2/3 */



#define IMELAR				0x0030	/* IMEAR on R-Car Gen2 */

#define IMELAR				0x0030		/* R-Car Gen2/3, IMEAR on R-Car Gen2 */

#define IMEUAR				0x0034		/* R-Car Gen3 only */



/* uTLB registers */

#define IMUCTR(n)			((n) < 32 ? IMUCTR0(n) : IMUCTR32(n))

#define IMUCTR0(n)			(0x0300 + ((n) * 16))

#define IMUCTR32(n)			(0x0600 + (((n) - 32) * 16))

#define IMUCTR_TTSEL_MMU(n)		((n) << 4)

#define IMUCTR_FLUSH			(1 << 1)

#define IMUCTR_MMUEN			(1 << 0)

#define IMUCTR0(n)			(0x0300 + ((n) * 16))		/* R-Car Gen2/3 */

#define IMUCTR32(n)			(0x0600 + (((n) - 32) * 16))	/* R-Car Gen3 only */

#define IMUCTR_TTSEL_MMU(n)		((n) << 4)	/* R-Car Gen2/3 */

#define IMUCTR_FLUSH			(1 << 1)	/* R-Car Gen2/3 */

#define IMUCTR_MMUEN			(1 << 0)	/* R-Car Gen2/3 */



#define IMUASID(n)			((n) < 32 ? IMUASID0(n) : IMUASID32(n))

#define IMUASID0(n)			(0x0308 + ((n) * 16))

#define IMUASID32(n)			(0x0608 + (((n) - 32) * 16))

#define IMUASID0(n)			(0x0308 + ((n) * 16))		/* R-Car Gen2/3 */

#define IMUASID32(n)			(0x0608 + (((n) - 32) * 16))	/* R-Car Gen3 only */



/* -----------------------------------------------------------------------------

 * Root device handling

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