drm/amd/powerplay: avoid disabling ECC if RAS is enabled for VEGA20 (df9331e5) · Commits · 戴 / test

Program THM_BACO_CNTL.SOC_DOMAIN_IDLE=1 will tell VBIOS to disable ECC when BACO exit. This can save BACO exit time by PSP on none-ECC SKU. Drop the setting for ECC supported SKU. Signed-off-by:

Le Ma <le.ma@amd.com> Reviewed-by:

Alex Deucher <alexander.deucher@amd.com> Reviewed-by:

Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:

Alex Deucher <alexander.deucher@amd.com>

drivers/gpu/drm/amd/powerplay/hwmgr/vega20_baco.c

+7 −5

Original line number	Diff line number	Diff line
		@@ -29,7 +29,7 @@
		#include "vega20_baco.h"
		#include "vega20_smumgr.h"


		#include "amdgpu_ras.h"

		static const struct soc15_baco_cmd_entry clean_baco_tbl[] =
		{
		@@ -74,6 +74,7 @@ int vega20_baco_get_state(struct pp_hwmgr hwmgr, enum BACO_STATE state)
		int vega20_baco_set_state(struct pp_hwmgr *hwmgr, enum BACO_STATE state)
		{
		struct amdgpu_device adev = (struct amdgpu_device )(hwmgr->adev);
		struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
		enum BACO_STATE cur_state;
		uint32_t data;

		@@ -84,10 +85,11 @@ int vega20_baco_set_state(struct pp_hwmgr *hwmgr, enum BACO_STATE state)
		return 0;

		if (state == BACO_STATE_IN) {
		if (!ras \|\| !ras->supported) {
		data = RREG32_SOC15(THM, 0, mmTHM_BACO_CNTL);
		data \|= 0x80000000;
		WREG32_SOC15(THM, 0, mmTHM_BACO_CNTL, data);

		}

		if(smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_EnterBaco, 0))
		return -EINVAL;

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