Commit df80bfd3 authored by Horia Geantă's avatar Horia Geantă Committed by Herbert Xu
Browse files

crypto: caam/jr - update gcm detection logic 



GCM detection logic has to change for two reasons:
-some CAAM instantiations with Era < 10, even though they have AES LP,
they now support GCM mode
-Era 10 upwards, there is a dedicated bit in AESA_VERSION[AESA_MISC]
field for GCM support

For Era 9 and earlier, all AES accelerator versions support GCM,
except for AES LP (CHAVID_LS[AESVID]=3) with revision CRNR[AESRN] < 8.

For Era 10 and later, bit 9 of the AESA_VERSION register should be used
to detect GCM support in AES accelerator.

Note: caam/qi and caam/qi2 are drivers for QI (Queue Interface), which
is used in DPAA-based SoCs; for now, we rely on CAAM having an AES HP
and this AES accelerator having support for GCM.

Signed-off-by: default avatarHoria Geantă <horia.geanta@nxp.com>
Reviewed-by: default avatarIuliana Prodan <iuliana.prodan@nxp.com>
Signed-off-by: default avatarHerbert Xu <herbert@gondor.apana.org.au>
parent 6ddc8e31

drivers/crypto/caam/caamalg.c

+11 −7
Original line number Diff line number Diff line
@@ -3493,7 +3493,7 @@ static int __init caam_algapi_init(void) 
	u32 aes_vid, aes_inst, des_inst, md_vid, md_inst, ccha_inst, ptha_inst;

	u32 arc4_inst;

	unsigned int md_limit = SHA512_DIGEST_SIZE;

	bool registered = false;

	bool registered = false, gcm_support;



	dev_node = of_find_compatible_node(NULL, NULL, "fsl,sec-v4.0");

	if (!dev_node) {
@@ -3526,7 +3526,7 @@ static int __init caam_algapi_init(void) 
	 * First, detect presence and attributes of DES, AES, and MD blocks.

	 */

	if (priv->era < 10) {

		u32 cha_vid, cha_inst;

		u32 cha_vid, cha_inst, aes_rn;



		cha_vid = rd_reg32(&priv->ctrl->perfmon.cha_id_ls);

		aes_vid = cha_vid & CHA_ID_LS_AES_MASK;
@@ -3541,6 +3541,10 @@ static int __init caam_algapi_init(void) 
			    CHA_ID_LS_ARC4_SHIFT;

		ccha_inst = 0;

		ptha_inst = 0;



		aes_rn = rd_reg32(&priv->ctrl->perfmon.cha_rev_ls) &

			 CHA_ID_LS_AES_MASK;

		gcm_support = !(aes_vid == CHA_VER_VID_AES_LP && aes_rn < 8);

	} else {

		u32 aesa, mdha;
@@ -3556,6 +3560,8 @@ static int __init caam_algapi_init(void) 
		ccha_inst = rd_reg32(&priv->ctrl->vreg.ccha) & CHA_VER_NUM_MASK;

		ptha_inst = rd_reg32(&priv->ctrl->vreg.ptha) & CHA_VER_NUM_MASK;

		arc4_inst = rd_reg32(&priv->ctrl->vreg.afha) & CHA_VER_NUM_MASK;



		gcm_support = aesa & CHA_VER_MISC_AES_GCM;

	}



	/* If MD is present, limit digest size based on LP256 */
@@ -3628,11 +3634,9 @@ static int __init caam_algapi_init(void) 
		if (c2_alg_sel == OP_ALG_ALGSEL_POLY1305 && !ptha_inst)

			continue;



		/*

		 * Check support for AES algorithms not available

		 * on LP devices.

		 */

		if (aes_vid  == CHA_VER_VID_AES_LP && alg_aai == OP_ALG_AAI_GCM)

		/* Skip GCM algorithms if not supported by device */

		if (c1_alg_sel == OP_ALG_ALGSEL_AES &&

		    alg_aai == OP_ALG_AAI_GCM && !gcm_support)

			continue;



		/*

drivers/crypto/caam/regs.h

+3 −0
Original line number Diff line number Diff line
@@ -261,6 +261,9 @@ struct version_regs { 
#define CHA_VER_VID_SHIFT	24

#define CHA_VER_VID_MASK	(0xffull << CHA_VER_VID_SHIFT)



/* CHA Miscellaneous Information - AESA_MISC specific */

#define CHA_VER_MISC_AES_GCM	BIT(1 + CHA_VER_MISC_SHIFT)



/*

 * caam_perfmon - Performance Monitor/Secure Memory Status/

 *                CAAM Global Status/Component Version IDs

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