Merge branch 'x86-mce-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip (df58bee2) · Commits · 戴 / test

Documentation/feature-removal-schedule.txt

+0 −10

Original line number	Diff line number	Diff line
		@@ -428,16 +428,6 @@ Who: Johannes Berg <johannes@sipsolutions.net>

		----------------------------

		What: CONFIG_X86_OLD_MCE
		When: 2.6.32
		Why: Remove the old legacy 32bit machine check code. This has been
		superseded by the newer machine check code from the 64bit port,
		but the old version has been kept around for easier testing. Note this
		doesn't impact the old P5 and WinChip machine check handlers.
		Who: Andi Kleen <andi@firstfloor.org>

		----------------------------

		What: lock_policy_rwsem_* and unlock_policy_rwsem_* will not be
		exported interface anymore.
		When: 2.6.33

arch/x86/Kconfig

+9 −53

Original line number	Diff line number	Diff line
		@@ -783,41 +783,17 @@ config X86_REROUTE_FOR_BROKEN_BOOT_IRQS
		increased on these systems.

		config X86_MCE
		bool "Machine Check Exception"
		bool "Machine Check / overheating reporting"
		---help---
		Machine Check Exception support allows the processor to notify the
		kernel if it detects a problem (e.g. overheating, component failure).
		Machine Check support allows the processor to notify the
		kernel if it detects a problem (e.g. overheating, data corruption).
		The action the kernel takes depends on the severity of the problem,
		ranging from a warning message on the console, to halting the machine.
		Your processor must be a Pentium or newer to support this - check the
		flags in /proc/cpuinfo for mce. Note that some older Pentium systems
		have a design flaw which leads to false MCE events - hence MCE is
		disabled on all P5 processors, unless explicitly enabled with "mce"
		as a boot argument. Similarly, if MCE is built in and creates a
		problem on some new non-standard machine, you can boot with "nomce"
		to disable it. MCE support simply ignores non-MCE processors like
		the 386 and 486, so nearly everyone can say Y here.

		config X86_OLD_MCE
		depends on X86_32 && X86_MCE
		bool "Use legacy machine check code (will go away)"
		default n
		select X86_ANCIENT_MCE
		---help---
		Use the old i386 machine check code. This is merely intended for
		testing in a transition period. Try this if you run into any machine
		check related software problems, but report the problem to
		linux-kernel. When in doubt say no.

		config X86_NEW_MCE
		depends on X86_MCE
		bool
		default y if (!X86_OLD_MCE && X86_32) \|\| X86_64
		ranging from warning messages to halting the machine.

		config X86_MCE_INTEL
		def_bool y
		prompt "Intel MCE features"
		depends on X86_NEW_MCE && X86_LOCAL_APIC
		depends on X86_MCE && X86_LOCAL_APIC
		---help---
		Additional support for intel specific MCE features such as
		the thermal monitor.
		@@ -825,14 +801,14 @@ config X86_MCE_INTEL
		config X86_MCE_AMD
		def_bool y
		prompt "AMD MCE features"
		depends on X86_NEW_MCE && X86_LOCAL_APIC
		depends on X86_MCE && X86_LOCAL_APIC
		---help---
		Additional support for AMD specific MCE features such as
		the DRAM Error Threshold.

		config X86_ANCIENT_MCE
		def_bool n
		depends on X86_32
		depends on X86_32 && X86_MCE
		prompt "Support for old Pentium 5 / WinChip machine checks"
		---help---
		Include support for machine check handling on old Pentium 5 or WinChip
		@@ -845,36 +821,16 @@ config X86_MCE_THRESHOLD
		default y

		config X86_MCE_INJECT
		depends on X86_NEW_MCE
		depends on X86_MCE
		tristate "Machine check injector support"
		---help---
		Provide support for injecting machine checks for testing purposes.
		If you don't know what a machine check is and you don't do kernel
		QA it is safe to say n.

		config X86_MCE_NONFATAL
		tristate "Check for non-fatal errors on AMD Athlon/Duron / Intel Pentium 4"
		depends on X86_OLD_MCE
		---help---
		Enabling this feature starts a timer that triggers every 5 seconds which
		will look at the machine check registers to see if anything happened.
		Non-fatal problems automatically get corrected (but still logged).
		Disable this if you don't want to see these messages.
		Seeing the messages this option prints out may be indicative of dying
		or out-of-spec (ie, overclocked) hardware.
		This option only does something on certain CPUs.
		(AMD Athlon/Duron and Intel Pentium 4)

		config X86_MCE_P4THERMAL
		bool "check for P4 thermal throttling interrupt."
		depends on X86_OLD_MCE && X86_MCE && (X86_UP_APIC \|\| SMP)
		---help---
		Enabling this feature will cause a message to be printed when the P4
		enters thermal throttling.

		config X86_THERMAL_VECTOR
		def_bool y
		depends on X86_MCE_P4THERMAL \|\| X86_MCE_INTEL
		depends on X86_MCE_INTEL

		config VM86
		bool "Enable VM86 support" if EMBEDDED

arch/x86/include/asm/entry_arch.h

+1 −1

Original line number	Diff line number	Diff line
		@@ -61,7 +61,7 @@ BUILD_INTERRUPT(thermal_interrupt,THERMAL_APIC_VECTOR)
		BUILD_INTERRUPT(threshold_interrupt,THRESHOLD_APIC_VECTOR)
		#endif

		#ifdef CONFIG_X86_NEW_MCE
		#ifdef CONFIG_X86_MCE
		BUILD_INTERRUPT(mce_self_interrupt,MCE_SELF_VECTOR)
		#endif

arch/x86/include/asm/mce.h

+15 −17

Original line number	Diff line number	Diff line
		@@ -9,7 +9,7 @@
		*/

		#define MCG_BANKCNT_MASK 0xff /* Number of Banks */
		#define MCG_CTL_P (1ULL<<8) /* MCG_CAP register available */
		#define MCG_CTL_P (1ULL<<8) /* MCG_CTL register available */
		#define MCG_EXT_P (1ULL<<9) /* Extended registers available */
		#define MCG_CMCI_P (1ULL<<10) /* CMCI supported */
		#define MCG_EXT_CNT_MASK 0xff0000 /* Number of Extended registers */
		@@ -38,6 +38,14 @@
		#define MCM_ADDR_MEM 3 /* memory address */
		#define MCM_ADDR_GENERIC 7 /* generic */

		#define MCJ_CTX_MASK 3
		#define MCJ_CTX(flags) ((flags) & MCJ_CTX_MASK)
		#define MCJ_CTX_RANDOM 0 /* inject context: random */
		#define MCJ_CTX_PROCESS 1 /* inject context: process */
		#define MCJ_CTX_IRQ 2 /* inject context: IRQ */
		#define MCJ_NMI_BROADCAST 4 /* do NMI broadcasting */
		#define MCJ_EXCEPTION 8 /* raise as exception */

		/* Fields are zero when not available */
		struct mce {
		__u64 status;
		@@ -48,8 +56,8 @@ struct mce {
		__u64 tsc; /* cpu time stamp counter */
		__u64 time; /* wall time_t when error was detected */
		__u8 cpuvendor; /* cpu vendor as encoded in system.h */
		__u8 pad1;
		__u16 pad2;
		__u8 inject_flags; /* software inject flags */
		__u16 pad;
		__u32 cpuid; /* CPUID 1 EAX */
		__u8 cs; /* code segment */
		__u8 bank; /* machine check bank */
		@@ -115,13 +123,6 @@ void mcheck_init(struct cpuinfo_x86 *c);
		static inline void mcheck_init(struct cpuinfo_x86 *c) {}
		#endif

		#ifdef CONFIG_X86_OLD_MCE
		extern int nr_mce_banks;
		void amd_mcheck_init(struct cpuinfo_x86 *c);
		void intel_p4_mcheck_init(struct cpuinfo_x86 *c);
		void intel_p6_mcheck_init(struct cpuinfo_x86 *c);
		#endif

		#ifdef CONFIG_X86_ANCIENT_MCE
		void intel_p5_mcheck_init(struct cpuinfo_x86 *c);
		void winchip_mcheck_init(struct cpuinfo_x86 *c);
		@@ -137,10 +138,11 @@ void mce_log(struct mce *m);
		DECLARE_PER_CPU(struct sys_device, mce_dev);

		/*
		* To support more than 128 would need to escape the predefined
		* Linux defined extended banks first.
		* Maximum banks number.
		* This is the limit of the current register layout on
		* Intel CPUs.
		*/
		#define MAX_NR_BANKS (MCE_EXTENDED_BANK - 1)
		#define MAX_NR_BANKS 32

		#ifdef CONFIG_X86_MCE_INTEL
		extern int mce_cmci_disabled;
		@@ -208,11 +210,7 @@ extern void (*threshold_cpu_callback)(unsigned long action, unsigned int cpu);

		void intel_init_thermal(struct cpuinfo_x86 *c);

		#ifdef CONFIG_X86_NEW_MCE
		void mce_log_therm_throt_event(__u64 status);
		#else
		static inline void mce_log_therm_throt_event(__u64 status) {}
		#endif

		#endif /* __KERNEL__ */
		#endif /* _ASM_X86_MCE_H */

arch/x86/include/asm/msr-index.h

+11 −0

Original line number	Diff line number	Diff line
		@@ -81,8 +81,15 @@
		#define MSR_IA32_MC0_ADDR 0x00000402
		#define MSR_IA32_MC0_MISC 0x00000403

		#define MSR_IA32_MCx_CTL(x) (MSR_IA32_MC0_CTL + 4*(x))
		#define MSR_IA32_MCx_STATUS(x) (MSR_IA32_MC0_STATUS + 4*(x))
		#define MSR_IA32_MCx_ADDR(x) (MSR_IA32_MC0_ADDR + 4*(x))
		#define MSR_IA32_MCx_MISC(x) (MSR_IA32_MC0_MISC + 4*(x))

		/* These are consecutive and not in the normal 4er MCE bank block */
		#define MSR_IA32_MC0_CTL2 0x00000280
		#define MSR_IA32_MCx_CTL2(x) (MSR_IA32_MC0_CTL2 + (x))

		#define CMCI_EN (1ULL << 30)
		#define CMCI_THRESHOLD_MASK 0xffffULL

		@@ -215,6 +222,10 @@

		#define THERM_STATUS_PROCHOT (1 << 0)

		#define MSR_THERM2_CTL 0x0000019d

		#define MSR_THERM2_CTL_TM_SELECT (1ULL << 16)

		#define MSR_IA32_MISC_ENABLE 0x000001a0

		/* MISC_ENABLE bits: architectural */

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