Commit df3f61d2 authored by Jonathan Marek's avatar Jonathan Marek Committed by Stephen Boyd
Browse files

dt-bindings: clock: add SM8150 QCOM video clock bindings



Add device tree bindings for video clock controller for SM8150 SoCs.

Signed-off-by: default avatarJonathan Marek <jonathan@marek.ca>
Reviewed-by: default avatarRob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20200923160635.28370-3-jonathan@marek.ca


Signed-off-by: default avatarStephen Boyd <sboyd@kernel.org>
parent 70d795d2
Loading
Loading
Loading
Loading
+3 −1
Original line number Diff line number Diff line
@@ -11,17 +11,19 @@ maintainers:

description: |
  Qualcomm video clock control module which supports the clocks, resets and
  power domains on SDM845/SC7180.
  power domains on SDM845/SC7180/SM8150.

  See also:
    dt-bindings/clock/qcom,videocc-sc7180.h
    dt-bindings/clock/qcom,videocc-sdm845.h
    dt-bindings/clock/qcom,videocc-sm8150.h

properties:
  compatible:
    enum:
      - qcom,sc7180-videocc
      - qcom,sdm845-videocc
      - qcom,sm8150-videocc

  clocks:
    items:
+25 −0
Original line number Diff line number Diff line
/* SPDX-License-Identifier: GPL-2.0-only */
/*
 * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved.
 */

#ifndef _DT_BINDINGS_CLK_QCOM_VIDEO_CC_SM8150_H
#define _DT_BINDINGS_CLK_QCOM_VIDEO_CC_SM8150_H

/* VIDEO_CC clocks */
#define VIDEO_CC_IRIS_AHB_CLK		0
#define VIDEO_CC_IRIS_CLK_SRC		1
#define VIDEO_CC_MVS0_CORE_CLK		2
#define VIDEO_CC_MVS1_CORE_CLK		3
#define VIDEO_CC_MVSC_CORE_CLK		4
#define VIDEO_CC_PLL0			5

/* VIDEO_CC Resets */
#define VIDEO_CC_MVSC_CORE_CLK_BCR	0

/* VIDEO_CC GDSCRs */
#define VENUS_GDSC			0
#define VCODEC0_GDSC			1
#define VCODEC1_GDSC			2

#endif