Commit df013ffb authored by Huang Ying's avatar Huang Ying Committed by Len Brown
Browse files

Add Kconfig option ARCH_HAVE_NMI_SAFE_CMPXCHG 



cmpxchg() is widely used by lockless code, including NMI-safe lockless
code.  But on some architectures, the cmpxchg() implementation is not
NMI-safe, on these architectures the lockless code may need a
spin_trylock_irqsave() based implementation.

This patch adds a Kconfig option: ARCH_HAVE_NMI_SAFE_CMPXCHG, so that
NMI-safe lockless code can depend on it or provide different
implementation according to it.

On many architectures, cmpxchg is only NMI-safe for several specific
operand sizes. So, ARCH_HAVE_NMI_SAFE_CMPXCHG define in this patch
only guarantees cmpxchg is NMI-safe for sizeof(unsigned long).

Signed-off-by: default avatarHuang Ying <ying.huang@intel.com>
Acked-by: default avatarMike Frysinger <vapier@gentoo.org>
Acked-by: default avatarPaul Mundt <lethal@linux-sh.org>
Acked-by: default avatarHans-Christian Egtvedt <hans-christian.egtvedt@atmel.com>
Acked-by: default avatarBenjamin Herrenschmidt <benh@kernel.crashing.org>
Acked-by: default avatarChris Metcalf <cmetcalf@tilera.com>
Acked-by: default avatarRichard Henderson <rth@twiddle.net>
CC: Mikael Starvik <starvik@axis.com>
Acked-by: default avatarDavid Howells <dhowells@redhat.com>
CC: Yoshinori Sato <ysato@users.sourceforge.jp>
CC: Tony Luck <tony.luck@intel.com>
CC: Hirokazu Takata <takata@linux-m32r.org>
CC: Geert Uytterhoeven <geert@linux-m68k.org>
CC: Michal Simek <monstr@monstr.eu>
Acked-by: default avatarRalf Baechle <ralf@linux-mips.org>
CC: Kyle McMartin <kyle@mcmartin.ca>
CC: Martin Schwidefsky <schwidefsky@de.ibm.com>
CC: Chen Liqin <liqin.chen@sunplusct.com>
CC: "David S. Miller" <davem@davemloft.net>
CC: Ingo Molnar <mingo@redhat.com>
CC: Chris Zankel <chris@zankel.net>
Signed-off-by: default avatarLen Brown <len.brown@intel.com>
parent 9fb0bfe1

arch/Kconfig

+3 −0
Original line number Original line Diff line number Diff line
@@ -178,4 +178,7 @@ config HAVE_ARCH_MUTEX_CPU_RELAX 
config HAVE_RCU_TABLE_FREE

config HAVE_RCU_TABLE_FREE

	bool

	bool





config ARCH_HAVE_NMI_SAFE_CMPXCHG

	bool



source "kernel/gcov/Kconfig"
 
source "kernel/gcov/Kconfig"

arch/alpha/Kconfig

+1 −0
Original line number Original line Diff line number Diff line
@@ -13,6 +13,7 @@ config ALPHA 
	select AUTO_IRQ_AFFINITY if SMP

	select AUTO_IRQ_AFFINITY if SMP

	select GENERIC_IRQ_SHOW

	select GENERIC_IRQ_SHOW

	select ARCH_WANT_OPTIONAL_GPIOLIB

	select ARCH_WANT_OPTIONAL_GPIOLIB

	select ARCH_HAVE_NMI_SAFE_CMPXCHG

	help

	help

	  The Alpha is a 64-bit general-purpose processor designed and

	  The Alpha is a 64-bit general-purpose processor designed and

	  marketed by the Digital Equipment Corporation of blessed memory,

	  marketed by the Digital Equipment Corporation of blessed memory,

arch/avr32/Kconfig

+1 −0
Original line number Original line Diff line number Diff line
@@ -10,6 +10,7 @@ config AVR32 
	select GENERIC_IRQ_PROBE

	select GENERIC_IRQ_PROBE

	select HARDIRQS_SW_RESEND

	select HARDIRQS_SW_RESEND

	select GENERIC_IRQ_SHOW

	select GENERIC_IRQ_SHOW

	select ARCH_HAVE_NMI_SAFE_CMPXCHG

	help

	help

	  AVR32 is a high-performance 32-bit RISC microprocessor core,

	  AVR32 is a high-performance 32-bit RISC microprocessor core,

	  designed for cost-sensitive embedded applications, with particular

	  designed for cost-sensitive embedded applications, with particular

arch/frv/Kconfig

+1 −0
Original line number Original line Diff line number Diff line
@@ -7,6 +7,7 @@ config FRV 
	select HAVE_PERF_EVENTS

	select HAVE_PERF_EVENTS

	select HAVE_GENERIC_HARDIRQS

	select HAVE_GENERIC_HARDIRQS

	select GENERIC_IRQ_SHOW

	select GENERIC_IRQ_SHOW

	select ARCH_HAVE_NMI_SAFE_CMPXCHG





config ZONE_DMA

config ZONE_DMA

	bool

	bool

arch/ia64/Kconfig

+1 −0
Original line number Original line Diff line number Diff line
@@ -27,6 +27,7 @@ config IA64 
	select GENERIC_PENDING_IRQ if SMP

	select GENERIC_PENDING_IRQ if SMP

	select IRQ_PER_CPU

	select IRQ_PER_CPU

	select GENERIC_IRQ_SHOW

	select GENERIC_IRQ_SHOW

	select ARCH_HAVE_NMI_SAFE_CMPXCHG

	default y

	default y

	help

	help

	  The Itanium Processor Family is Intel's 64-bit successor to

	  The Itanium Processor Family is Intel's 64-bit successor to

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