Commit def10853 authored by Fenghua Yu's avatar Fenghua Yu Committed by Thomas Gleixner
Browse files

x86/intel_rdt: Add two new resources for L2 Code and Data Prioritization (CDP) 



L2 data and L2 code are added as new resources in rdt_resources_all[]
and data in the resources are configured.

When L2 CDP is enabled, the schemata will have the two resources in
this format:
L2DATA:l2id0=xxxx;l2id1=xxxx;....
L2CODE:l2id0=xxxx;l2id1=xxxx;....

xxxx represent CBM (Cache Bit Mask) values in the schemata, similar to all
others (L2 CAT/L3 CAT/L3 CDP).

Signed-off-by: default avatarFenghua Yu <fenghua.yu@intel.com>
Signed-off-by: default avatarThomas Gleixner <tglx@linutronix.de>
Cc: "Ravi V Shankar" <ravi.v.shankar@intel.com>
Cc: "Tony Luck" <tony.luck@intel.com>
Cc: Vikas" <vikas.shivappa@intel.com>
Cc: Sai Praneeth" <sai.praneeth.prakhya@intel.com>
Cc: Reinette" <reinette.chatre@intel.com>
Link: https://lkml.kernel.org/r/1513810644-78015-5-git-send-email-fenghua.yu@intel.com
parent a511e793

arch/x86/kernel/cpu/intel_rdt.c

+56 −10
Original line number Diff line number Diff line
@@ -135,6 +135,40 @@ struct rdt_resource rdt_resources_all[] = { 
		.format_str		= "%d=%0*x",

		.fflags			= RFTYPE_RES_CACHE,

	},

	[RDT_RESOURCE_L2DATA] =

	{

		.rid			= RDT_RESOURCE_L2DATA,

		.name			= "L2DATA",

		.domains		= domain_init(RDT_RESOURCE_L2DATA),

		.msr_base		= IA32_L2_CBM_BASE,

		.msr_update		= cat_wrmsr,

		.cache_level		= 2,

		.cache = {

			.min_cbm_bits	= 1,

			.cbm_idx_mult	= 2,

			.cbm_idx_offset	= 0,

		},

		.parse_ctrlval		= parse_cbm,

		.format_str		= "%d=%0*x",

		.fflags			= RFTYPE_RES_CACHE,

	},

	[RDT_RESOURCE_L2CODE] =

	{

		.rid			= RDT_RESOURCE_L2CODE,

		.name			= "L2CODE",

		.domains		= domain_init(RDT_RESOURCE_L2CODE),

		.msr_base		= IA32_L2_CBM_BASE,

		.msr_update		= cat_wrmsr,

		.cache_level		= 2,

		.cache = {

			.min_cbm_bits	= 1,

			.cbm_idx_mult	= 2,

			.cbm_idx_offset	= 1,

		},

		.parse_ctrlval		= parse_cbm,

		.format_str		= "%d=%0*x",

		.fflags			= RFTYPE_RES_CACHE,

	},

	[RDT_RESOURCE_MBA] =

	{

		.rid			= RDT_RESOURCE_MBA,
@@ -259,15 +293,15 @@ static void rdt_get_cache_alloc_cfg(int idx, struct rdt_resource *r) 
	r->alloc_enabled = true;

}



static void rdt_get_cdp_l3_config(int type)

static void rdt_get_cdp_config(int level, int type)

{

	struct rdt_resource *r_l3 = &rdt_resources_all[RDT_RESOURCE_L3];

	struct rdt_resource *r_l = &rdt_resources_all[level];

	struct rdt_resource *r = &rdt_resources_all[type];



	r->num_closid = r_l3->num_closid / 2;

	r->cache.cbm_len = r_l3->cache.cbm_len;

	r->default_ctrl = r_l3->default_ctrl;

	r->cache.shareable_bits = r_l3->cache.shareable_bits;

	r->num_closid = r_l->num_closid / 2;

	r->cache.cbm_len = r_l->cache.cbm_len;

	r->default_ctrl = r_l->default_ctrl;

	r->cache.shareable_bits = r_l->cache.shareable_bits;

	r->data_width = (r->cache.cbm_len + 3) / 4;

	r->alloc_capable = true;

	/*
@@ -277,6 +311,18 @@ static void rdt_get_cdp_l3_config(int type) 
	r->alloc_enabled = false;

}



static void rdt_get_cdp_l3_config(void)

{

	rdt_get_cdp_config(RDT_RESOURCE_L3, RDT_RESOURCE_L3DATA);

	rdt_get_cdp_config(RDT_RESOURCE_L3, RDT_RESOURCE_L3CODE);

}



static void rdt_get_cdp_l2_config(void)

{

	rdt_get_cdp_config(RDT_RESOURCE_L2, RDT_RESOURCE_L2DATA);

	rdt_get_cdp_config(RDT_RESOURCE_L2, RDT_RESOURCE_L2CODE);

}



static int get_cache_id(int cpu, int level)

{

	struct cpu_cacheinfo *ci = get_cpu_cacheinfo(cpu);
@@ -729,15 +775,15 @@ static __init bool get_rdt_alloc_resources(void) 


	if (rdt_cpu_has(X86_FEATURE_CAT_L3)) {

		rdt_get_cache_alloc_cfg(1, &rdt_resources_all[RDT_RESOURCE_L3]);

		if (rdt_cpu_has(X86_FEATURE_CDP_L3)) {

			rdt_get_cdp_l3_config(RDT_RESOURCE_L3DATA);

			rdt_get_cdp_l3_config(RDT_RESOURCE_L3CODE);

		}

		if (rdt_cpu_has(X86_FEATURE_CDP_L3))

			rdt_get_cdp_l3_config();

		ret = true;

	}

	if (rdt_cpu_has(X86_FEATURE_CAT_L2)) {

		/* CPUID 0x10.2 fields are same format at 0x10.1 */

		rdt_get_cache_alloc_cfg(2, &rdt_resources_all[RDT_RESOURCE_L2]);

		if (rdt_cpu_has(X86_FEATURE_CDP_L2))

			rdt_get_cdp_l2_config();

		ret = true;

	}

arch/x86/kernel/cpu/intel_rdt.h

+2 −0
Original line number Diff line number Diff line
@@ -357,6 +357,8 @@ enum { 
	RDT_RESOURCE_L3DATA,

	RDT_RESOURCE_L3CODE,

	RDT_RESOURCE_L2,

	RDT_RESOURCE_L2DATA,

	RDT_RESOURCE_L2CODE,

	RDT_RESOURCE_MBA,



	/* Must be the last */

CRA Git | Maintained and supported by SUSTech CRA and CCSE