Commit dec78805 authored by Chengming Gui's avatar Chengming Gui Committed by Alex Deucher
Browse files

drm/amd/amdgpu: Correct gfx10's CG sequence 



Incorrect CG sequence will cause gfx timedout,
if we keep switching power profile mode
(enter profile mod such as PEAK will disable CG,
exit profile mode EXIT will enable CG)
when run Vulkan test case(case used for test: vkexample).

Signed-off-by: default avatarChengming Gui <Jack.Gui@amd.com>
Reviewed-by: default avatarKenneth Feng <kenneth.feng@amd.com>
Acked-by: default avatarEvan Quan <evan.quan@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 5932d260

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

+15 −8
Original line number Diff line number Diff line
@@ -4104,6 +4104,12 @@ static void gfx_v10_0_update_medium_grain_clock_gating(struct amdgpu_device *ade 


	/* It is disabled by HW by default */

	if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {

		/* 0 - Disable some blocks' MGCG */

		WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000);

		WREG32_SOC15(GC, 0, mmCGTT_WD_CLK_CTRL, 0xff000000);

		WREG32_SOC15(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xff000000);

		WREG32_SOC15(GC, 0, mmCGTT_IA_CLK_CTRL, 0xff000000);



		/* 1 - RLC_CGTT_MGCG_OVERRIDE */

		def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);

		data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
@@ -4143,19 +4149,20 @@ static void gfx_v10_0_update_medium_grain_clock_gating(struct amdgpu_device *ade 
		if (def != data)

			WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);



		/* 2 - disable MGLS in RLC */

		/* 2 - disable MGLS in CP */

		data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);

		if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) {

			data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;

			WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data);

		}



		/* 3 - disable MGLS in RLC */

		data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);

		if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) {

			data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;

			WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data);

		}



		/* 3 - disable MGLS in CP */

		data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);

		if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) {

			data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;

			WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data);

		}

	}

}
@@ -4266,7 +4273,7 @@ static int gfx_v10_0_update_gfx_clock_gating(struct amdgpu_device *adev, 
		/* ===  CGCG /CGLS for GFX 3D Only === */

		gfx_v10_0_update_3d_clock_gating(adev, enable);

		/* ===  MGCG + MGLS === */

		gfx_v10_0_update_medium_grain_clock_gating(adev, enable);

		/* gfx_v10_0_update_medium_grain_clock_gating(adev, enable); */

	}



	if (adev->cg_flags &

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