Commit de730f71 authored by Mike Marciniszyn's avatar Mike Marciniszyn Committed by Jason Gunthorpe
Browse files

IB/hfi1: Move chip specific functions to chip.c 

Move routines and defines associated with hdrq size validation to a chip
specific routine since the limits are specific to the device.

Fix incorrect value for min size 2 -> 32

CSR writes should also be in chip.c.

Create a chip routine to write the hdrq specific CSRs and call as
appropriate.

Link: https://lore.kernel.org/r/20200106134144.119356.74312.stgit@awfm-01.aw.intel.com


Reviewed-by: default avatarDennis Dalessandro <dennis.dalessandro@intel.com>
Reviewed-by: default avatarMichael J. Ruhl <michael.j.ruhl@intel.com>
Signed-off-by: default avatarMike Marciniszyn <mike.marciniszyn@intel.com>
Signed-off-by: default avatarKaike Wan <kaike.wan@intel.com>
Signed-off-by: default avatarDennis Dalessandro <dennis.dalessandro@intel.com>
Signed-off-by: default avatarJason Gunthorpe <jgg@mellanox.com>
parent 14e23bd6

drivers/infiniband/hw/hfi1/chip.c

+78 −0
Original line number Diff line number Diff line
@@ -11858,6 +11858,84 @@ static u32 encoded_size(u32 size) 
	return 0x1;	/* if invalid, go with the minimum size */

}



/**

 * encode_rcv_header_entry_size - return chip specific encoding for size

 * @size: size in dwords

 *

 * Convert a receive header entry size that to the encoding used in the CSR.

 *

 * Return a zero if the given size is invalid, otherwise the encoding.

 */

u8 encode_rcv_header_entry_size(u8 size)

{

	/* there are only 3 valid receive header entry sizes */

	if (size == 2)

		return 1;

	if (size == 16)

		return 2;

	if (size == 32)

		return 4;

	return 0; /* invalid */

}



/**

 * hfi1_validate_rcvhdrcnt - validate hdrcnt

 * @dd: the device data

 * @thecnt: the header count

 */

int hfi1_validate_rcvhdrcnt(struct hfi1_devdata *dd, uint thecnt)

{

	if (thecnt <= HFI1_MIN_HDRQ_EGRBUF_CNT) {

		dd_dev_err(dd, "Receive header queue count too small\n");

		return -EINVAL;

	}



	if (thecnt > HFI1_MAX_HDRQ_EGRBUF_CNT) {

		dd_dev_err(dd,

			   "Receive header queue count cannot be greater than %u\n",

			   HFI1_MAX_HDRQ_EGRBUF_CNT);

		return -EINVAL;

	}



	if (thecnt % HDRQ_INCREMENT) {

		dd_dev_err(dd, "Receive header queue count %d must be divisible by %lu\n",

			   thecnt, HDRQ_INCREMENT);

		return -EINVAL;

	}



	return 0;

}



/**

 * set_hdrq_regs - set header queue registers for context

 * @dd: the device data

 * @ctxt: the context

 * @entsize: the dword entry size

 * @hdrcnt: the number of header entries

 */

void set_hdrq_regs(struct hfi1_devdata *dd, u8 ctxt, u8 entsize, u16 hdrcnt)

{

	u64 reg;



	reg = (((u64)hdrcnt >> HDRQ_SIZE_SHIFT) & RCV_HDR_CNT_CNT_MASK) <<

	      RCV_HDR_CNT_CNT_SHIFT;

	write_kctxt_csr(dd, ctxt, RCV_HDR_CNT, reg);

	reg = ((u64)encode_rcv_header_entry_size(entsize) &

	       RCV_HDR_ENT_SIZE_ENT_SIZE_MASK) <<

	      RCV_HDR_ENT_SIZE_ENT_SIZE_SHIFT;

	write_kctxt_csr(dd, ctxt, RCV_HDR_ENT_SIZE, reg);

	reg = ((u64)DEFAULT_RCVHDRSIZE & RCV_HDR_SIZE_HDR_SIZE_MASK) <<

	      RCV_HDR_SIZE_HDR_SIZE_SHIFT;

	write_kctxt_csr(dd, ctxt, RCV_HDR_SIZE, reg);



	/*

	 * Program dummy tail address for every receive context

	 * before enabling any receive context

	 */

	write_kctxt_csr(dd, ctxt, RCV_HDR_TAIL_ADDR,

			dd->rcvhdrtail_dummy_dma);

}



void hfi1_rcvctrl(struct hfi1_devdata *dd, unsigned int op,

		  struct hfi1_ctxtdata *rcd)

{

drivers/infiniband/hw/hfi1/chip.h

+6 −0
Original line number Diff line number Diff line
@@ -358,6 +358,8 @@ 
#define MAX_EAGER_BUFFER       (256 * 1024)

#define MAX_EAGER_BUFFER_TOTAL (64 * (1 << 20)) /* max per ctxt 64MB */

#define MAX_EXPECTED_BUFFER    (2048 * 1024)

#define HFI1_MIN_HDRQ_EGRBUF_CNT 32

#define HFI1_MAX_HDRQ_EGRBUF_CNT 16352



/*

 * Receive expected base and count and eager base and count increment -
@@ -699,6 +701,10 @@ static inline u32 chip_rcv_array_count(struct hfi1_devdata *dd) 
	return read_csr(dd, RCV_ARRAY_CNT);

}



u8 encode_rcv_header_entry_size(u8 size);

int hfi1_validate_rcvhdrcnt(struct hfi1_devdata *dd, uint thecnt);

void set_hdrq_regs(struct hfi1_devdata *dd, u8 ctxt, u8 entsize, u16 hdrcnt);



u64 create_pbc(struct hfi1_pportdata *ppd, u64 flags, int srate_mbs, u32 vl,

	       u32 dw_len);

drivers/infiniband/hw/hfi1/init.c

+3 −69
Original line number Diff line number Diff line
@@ -78,8 +78,6 @@ 
 */

#define HFI1_MIN_USER_CTXT_BUFCNT 7



#define HFI1_MIN_HDRQ_EGRBUF_CNT 2

#define HFI1_MAX_HDRQ_EGRBUF_CNT 16352

#define HFI1_MIN_EAGER_BUFFER_SIZE (4 * 1024) /* 4KB */

#define HFI1_MAX_EAGER_BUFFER_SIZE (256 * 1024) /* 256KB */
@@ -122,8 +120,6 @@ unsigned int user_credit_return_threshold = 33; /* default is 33% */ 
module_param(user_credit_return_threshold, uint, S_IRUGO);

MODULE_PARM_DESC(user_credit_return_threshold, "Credit return threshold for user send contexts, return when unreturned credits passes this many blocks (in percent of allocated blocks, 0 is off)");



static inline u64 encode_rcv_header_entry_size(u16 size);



DEFINE_XARRAY_FLAGS(hfi1_dev_table, XA_FLAGS_ALLOC | XA_FLAGS_LOCK_IRQ);



static int hfi1_create_kctxt(struct hfi1_devdata *dd,
@@ -510,23 +506,6 @@ void hfi1_free_ctxt(struct hfi1_ctxtdata *rcd) 
	hfi1_rcd_put(rcd);

}



/*

 * Convert a receive header entry size that to the encoding used in the CSR.

 *

 * Return a zero if the given size is invalid.

 */

static inline u64 encode_rcv_header_entry_size(u16 size)

{

	/* there are only 3 valid receive header entry sizes */

	if (size == 2)

		return 1;

	if (size == 16)

		return 2;

	else if (size == 32)

		return 4;

	return 0; /* invalid */

}



/*

 * Select the largest ccti value over all SLs to determine the intra-

 * packet gap for the link.
@@ -1611,29 +1590,6 @@ static void postinit_cleanup(struct hfi1_devdata *dd) 
	hfi1_free_devdata(dd);

}



static int init_validate_rcvhdrcnt(struct hfi1_devdata *dd, uint thecnt)

{

	if (thecnt <= HFI1_MIN_HDRQ_EGRBUF_CNT) {

		dd_dev_err(dd, "Receive header queue count too small\n");

		return -EINVAL;

	}



	if (thecnt > HFI1_MAX_HDRQ_EGRBUF_CNT) {

		dd_dev_err(dd,

			   "Receive header queue count cannot be greater than %u\n",

			   HFI1_MAX_HDRQ_EGRBUF_CNT);

		return -EINVAL;

	}



	if (thecnt % HDRQ_INCREMENT) {

		dd_dev_err(dd, "Receive header queue count %d must be divisible by %lu\n",

			   thecnt, HDRQ_INCREMENT);

		return -EINVAL;

	}



	return 0;

}



static int init_one(struct pci_dev *pdev, const struct pci_device_id *ent)

{

	int ret = 0, j, pidx, initfail;
@@ -1661,7 +1617,7 @@ static int init_one(struct pci_dev *pdev, const struct pci_device_id *ent) 
	}



	/* Validate some global module parameters */

	ret = init_validate_rcvhdrcnt(dd, rcvhdrcnt);

	ret = hfi1_validate_rcvhdrcnt(dd, rcvhdrcnt);

	if (ret)

		goto bail;
@@ -1842,7 +1798,6 @@ static void shutdown_one(struct pci_dev *pdev) 
int hfi1_create_rcvhdrq(struct hfi1_devdata *dd, struct hfi1_ctxtdata *rcd)

{

	unsigned amt;

	u64 reg;



	if (!rcd->rcvhdrq) {

		gfp_t gfp_flags;
@@ -1874,30 +1829,9 @@ int hfi1_create_rcvhdrq(struct hfi1_devdata *dd, struct hfi1_ctxtdata *rcd) 
				goto bail_free;

		}

	}

	/*

	 * These values are per-context:

	 *	RcvHdrCnt

	 *	RcvHdrEntSize

	 *	RcvHdrSize

	 */

	reg = ((u64)(rcd->rcvhdrq_cnt >> HDRQ_SIZE_SHIFT)

			& RCV_HDR_CNT_CNT_MASK)

		<< RCV_HDR_CNT_CNT_SHIFT;

	write_kctxt_csr(dd, rcd->ctxt, RCV_HDR_CNT, reg);

	reg = (encode_rcv_header_entry_size(rcd->rcvhdrqentsize)

			& RCV_HDR_ENT_SIZE_ENT_SIZE_MASK)

		<< RCV_HDR_ENT_SIZE_ENT_SIZE_SHIFT;

	write_kctxt_csr(dd, rcd->ctxt, RCV_HDR_ENT_SIZE, reg);

	reg = ((u64)DEFAULT_RCVHDRSIZE & RCV_HDR_SIZE_HDR_SIZE_MASK)

		<< RCV_HDR_SIZE_HDR_SIZE_SHIFT;

	write_kctxt_csr(dd, rcd->ctxt, RCV_HDR_SIZE, reg);



	/*

	 * Program dummy tail address for every receive context

	 * before enabling any receive context

	 */

	write_kctxt_csr(dd, rcd->ctxt, RCV_HDR_TAIL_ADDR,

			dd->rcvhdrtail_dummy_dma);

	set_hdrq_regs(rcd->dd, rcd->ctxt, rcd->rcvhdrqentsize,

		      rcd->rcvhdrq_cnt);



	return 0;

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