gma500: polish for completion of this phase (de64ac92) · Commits · 戴 / test

drivers/staging/gma500/mrst_crtc.c

+2 −2

Original line number	Diff line number	Diff line
		@@ -86,7 +86,7 @@ static const struct mrst_limit_t mrst_limit(struct drm_crtc crtc)
		{
		const struct mrst_limit_t *limit = NULL;
		struct drm_device *dev = crtc->dev;
		DRM_DRIVER_PRIVATE_T *dev_priv = dev->dev_private;
		struct drm_psb_private *dev_priv = dev->dev_private;

		if (psb_intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)
		\|\| psb_intel_pipe_has_type(crtc, INTEL_OUTPUT_MIPI)) {
		@@ -296,7 +296,7 @@ static int mrst_crtc_mode_set(struct drm_crtc *crtc,
		{
		struct drm_device *dev = crtc->dev;
		struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
		DRM_DRIVER_PRIVATE_T *dev_priv = dev->dev_private;
		struct drm_psb_private *dev_priv = dev->dev_private;
		int pipe = psb_intel_crtc->pipe;
		int fp_reg = (pipe == 0) ? MRST_FPA0 : FPB0;
		int dpll_reg = (pipe == 0) ? MRST_DPLL_A : DPLL_B;

drivers/staging/gma500/mrst_lvds.c

+1 −1

Original line number	Diff line number	Diff line
		@@ -46,7 +46,7 @@ static void mrst_lvds_set_power(struct drm_device *dev,
		struct psb_intel_output *output, bool on)
		{
		u32 pp_status;
		DRM_DRIVER_PRIVATE_T *dev_priv = dev->dev_private;
		struct drm_psb_private *dev_priv = dev->dev_private;
		PSB_DEBUG_ENTRY("\n");

		if (!gma_power_begin(dev, true))

drivers/staging/gma500/psb_2d.c

+1 −6

Original line number	Diff line number	Diff line
		/**************************************************************************
		* Copyright (c) 2007, Intel Corporation.
		* Copyright (c) 2007-2011, Intel Corporation.
		* All Rights Reserved.
		*
		* This program is free software; you can redistribute it and/or modify it
		@@ -396,8 +396,3 @@ int psbfb_sync(struct fb_info *info)
		out:
		return (busy) ? -EBUSY : 0;
		}

		/*
		info->fix.accel = FB_ACCEL_I830;
		info->flags = FBINFO_DEFAULT;
		*/

drivers/staging/gma500/psb_bl.c

+2 −2

Original line number	Diff line number	Diff line
		/*
		* psb backlight interface
		* GMA500 Backlight Interface
		*
		* Copyright (c) 2009, Intel Corporation.
		* Copyright (c) 2009-2011, Intel Corporation.
		*
		* This program is free software; you can redistribute it and/or modify it
		* under the terms and conditions of the GNU General Public License,

drivers/staging/gma500/psb_drm.h

+2 −88

Original line number	Diff line number	Diff line
		/**************************************************************************
		* Copyright (c) 2007, Intel Corporation.
		* Copyright (c) 2007-2011, Intel Corporation.
		* All Rights Reserved.
		* Copyright (c) 2008, Tungsten Graphics Inc. Cedar Park, TX., USA.
		* All Rights Reserved.
		@@ -22,84 +22,8 @@
		#ifndef _PSB_DRM_H_
		#define _PSB_DRM_H_

		#if defined(__linux__) && !defined(__KERNEL__)
		#include<stdint.h>
		#include <linux/types.h>
		#include "drm_mode.h"
		#endif

		#define DRM_PSB_SAREA_MAJOR 0
		#define DRM_PSB_SAREA_MINOR 2
		#define PSB_FIXED_SHIFT 16

		#define PSB_NUM_PIPE 3

		/*
		* Public memory types.
		*/

		typedef s32 psb_fixed;
		typedef u32 psb_ufixed;

		static inline s32 psb_int_to_fixed(int a)
		{
		return a * (1 << PSB_FIXED_SHIFT);
		}

		static inline u32 psb_unsigned_to_ufixed(unsigned int a)
		{
		return a << PSB_FIXED_SHIFT;
		}

		/Status of the command sent to the gfx device./
		typedef enum {
		DRM_CMD_SUCCESS,
		DRM_CMD_FAILED,
		DRM_CMD_HANG
		} drm_cmd_status_t;

		struct drm_psb_scanout {
		u32 buffer_id; /* DRM buffer object ID */
		u32 rotation; /* Rotation as in RR_rotation definitions */
		u32 stride; /* Buffer stride in bytes */
		u32 depth; /* Buffer depth in bits (NOT) bpp */
		u32 width; /* Buffer width in pixels */
		u32 height; /* Buffer height in lines */
		s32 transform[3][3]; /* Buffer composite transform */
		/* (scaling, rot, reflect) */
		};

		#define DRM_PSB_SAREA_OWNERS 16
		#define DRM_PSB_SAREA_OWNER_2D 0
		#define DRM_PSB_SAREA_OWNER_3D 1

		#define DRM_PSB_SAREA_SCANOUTS 3

		struct drm_psb_sarea {
		/* Track changes of this data structure */

		u32 major;
		u32 minor;

		/* Last context to touch part of hw */
		u32 ctx_owners[DRM_PSB_SAREA_OWNERS];

		/* Definition of front- and rotated buffers */
		u32 num_scanouts;
		struct drm_psb_scanout scanouts[DRM_PSB_SAREA_SCANOUTS];

		int planeA_x;
		int planeA_y;
		int planeA_w;
		int planeA_h;
		int planeB_x;
		int planeB_y;
		int planeB_w;
		int planeB_h;
		/* Number of active scanouts */
		u32 num_active_scanouts;
		};

		#define PSB_GPU_ACCESS_READ (1ULL << 32)
		#define PSB_GPU_ACCESS_WRITE (1ULL << 33)
		#define PSB_GPU_ACCESS_MASK (PSB_GPU_ACCESS_READ \| PSB_GPU_ACCESS_WRITE)
		@@ -223,20 +147,14 @@ struct drm_psb_register_rw_arg {

		#define DRM_PSB_KMS_OFF 0x00
		#define DRM_PSB_KMS_ON 0x01
		#define DRM_PSB_VT_LEAVE 0x02
		#define DRM_PSB_VT_ENTER 0x03
		#define DRM_PSB_EXTENSION 0x06
		#define DRM_PSB_SIZES 0x07
		#define DRM_PSB_FUSE_REG 0x08
		#define DRM_PSB_VBT 0x09
		#define DRM_PSB_DC_STATE 0x0A
		#define DRM_PSB_ADB 0x0B
		#define DRM_PSB_MODE_OPERATION 0x0C
		#define DRM_PSB_STOLEN_MEMORY 0x0D
		#define DRM_PSB_REGISTER_RW 0x0E
		#define DRM_PSB_GTT_MAP 0x0F
		#define DRM_PSB_GTT_UNMAP 0x10
		#define DRM_PSB_GETPAGEADDRS 0x11

		/**
		* NOTE: Add new commands here, but increment
		* the values below and increment their
		@@ -249,10 +167,6 @@ struct drm_psb_register_rw_arg {
		#define DRM_PVR_RESERVED4 0x15
		#define DRM_PVR_RESERVED5 0x16

		#define DRM_PSB_HIST_ENABLE 0x17
		#define DRM_PSB_HIST_STATUS 0x18
		#define DRM_PSB_UPDATE_GUARD 0x19
		#define DRM_PSB_INIT_COMM 0x1A
		#define DRM_PSB_DPST 0x1B
		#define DRM_PSB_GAMMA 0x1C
		#define DRM_PSB_DPST_BL 0x1D

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