Unverified Commit de4c2875 authored May 29, 2020 by Serge Semin Committed by Mark Brown May 29, 2020

spi: dw: Set xfer effective_speed_hz



Seeing DW APB SSI controller doesn't support setting the exactly
requested SPI bus frequency, but only a rounded frequency determined
by means of the odd-numbered half-worded reference clock divider,
it would be good to tune the SPI core up and initialize the current
transfer effective_speed_hz. By doing so the core will be able to
execute the xfer-related delays with better accuracy.

Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
Cc: Georgy Vlasov <Georgy.Vlasov@baikalelectronics.ru>
Cc: Ramil Zaripov <Ramil.Zaripov@baikalelectronics.ru>
Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Feng Tang <feng.tang@intel.com>
Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: linux-mips@vger.kernel.org
Cc: devicetree@vger.kernel.org
Link: https://lore.kernel.org/r/20200529131205.31838-2-Sergey.Semin@baikalelectronics.ru


Signed-off-by: Mark Brown <broonie@kernel.org>

parent b7d73cb6

drivers/spi/spi-dw.c

+1 −0

Original line number	Diff line number	Diff line
		@@ -352,6 +352,7 @@ static int dw_spi_transfer_one(struct spi_controller *master,
		spi_set_clk(dws, chip->clk_div);
		}

		transfer->effective_speed_hz = dws->max_freq / chip->clk_div;
		dws->n_bytes = DIV_ROUND_UP(transfer->bits_per_word, BITS_PER_BYTE);

		cr0 = dws->update_cr0(master, spi, transfer);

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