Commit de417d13 authored by David S. Miller's avatar David S. Miller
Browse files

Merge branch 'net-phy-broadcom-RGMII-delays-fixes' 



Florian Fainelli says:

====================
net: phy: broadcom: RGMII delays fixes

This patch series fixes the BCM54210E RGMII delay configuration which
could only have worked in a PHY_INTERFACE_MODE_RGMII configuration.
There is a forward declaration added such that the first patch can be
picked up for -stable and apply fine all the way back to when the bug
was introduced.

The second patch eliminates duplicated code that used a different kind
of logic and did not use existing constants defined.
====================

Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents 6d4e4ddc bea5d143

drivers/net/phy/broadcom.c

+4 −28
Original line number Diff line number Diff line
@@ -26,18 +26,13 @@ MODULE_DESCRIPTION("Broadcom PHY driver"); 
MODULE_AUTHOR("Maciej W. Rozycki");

MODULE_LICENSE("GPL");



static int bcm54xx_config_clock_delay(struct phy_device *phydev);



static int bcm54210e_config_init(struct phy_device *phydev)

{

	int val;



	val = bcm54xx_auxctl_read(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC);

	val &= ~MII_BCM54XX_AUXCTL_SHDWSEL_MISC_RGMII_SKEW_EN;

	val |= MII_BCM54XX_AUXCTL_MISC_WREN;

	bcm54xx_auxctl_write(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC, val);



	val = bcm_phy_read_shadow(phydev, BCM54810_SHD_CLK_CTL);

	val &= ~BCM54810_SHD_CLK_CTL_GTXCLK_EN;

	bcm_phy_write_shadow(phydev, BCM54810_SHD_CLK_CTL, val);

	bcm54xx_config_clock_delay(phydev);



	if (phydev->dev_flags & PHY_BRCM_EN_MASTER_MODE) {

		val = phy_read(phydev, MII_CTRL1000);
@@ -52,26 +47,7 @@ static int bcm54612e_config_init(struct phy_device *phydev) 
{

	int reg;



	/* Clear TX internal delay unless requested. */

	if ((phydev->interface != PHY_INTERFACE_MODE_RGMII_ID) &&

	    (phydev->interface != PHY_INTERFACE_MODE_RGMII_TXID)) {

		/* Disable TXD to GTXCLK clock delay (default set) */

		/* Bit 9 is the only field in shadow register 00011 */

		bcm_phy_write_shadow(phydev, 0x03, 0);

	}



	/* Clear RX internal delay unless requested. */

	if ((phydev->interface != PHY_INTERFACE_MODE_RGMII_ID) &&

	    (phydev->interface != PHY_INTERFACE_MODE_RGMII_RXID)) {

		reg = bcm54xx_auxctl_read(phydev,

					  MII_BCM54XX_AUXCTL_SHDWSEL_MISC);

		/* Disable RXD to RXC delay (default set) */

		reg &= ~MII_BCM54XX_AUXCTL_SHDWSEL_MISC_RGMII_SKEW_EN;

		/* Clear shadow selector field */

		reg &= ~MII_BCM54XX_AUXCTL_SHDWSEL_MASK;

		bcm54xx_auxctl_write(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC,

				     MII_BCM54XX_AUXCTL_MISC_WREN | reg);

	}

	bcm54xx_config_clock_delay(phydev);



	/* Enable CLK125 MUX on LED4 if ref clock is enabled. */

	if (!(phydev->dev_flags & PHY_BRCM_RX_REFCLK_UNUSED)) {

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