Commit de390bba authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus 

Pull MIPS update from Ralf Baechle:
 "This is the MIPS update for 3.7.

  A fair chunk of them are platform updates to the Cavium Octeon SOC
  (which involves machine generated header files of considerable size),
  Atheros ATH79xx, RMI aka Netlogic aka Broadcom XLP, Broadcom BCM63xx
  platforms.

  Support for the commercial MIPS simulator MIPSsim has been removed as
  MIPS Technologies is shifting away from this product and Qemu is
  offering various more powerful platforms.  The generic MIPS code can
  now also probe for no-execute / write-only TLB features implemented
  without the full SmartMIPS extension as permitted by the latest MIPS
  processor architecture.  Lots of small changes to generic code."

* 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (78 commits)
  MIPS: ath79: Fix CPU/DDR frequency calculation for SRIF PLLs
  MIPS: ath79: use correct fractional dividers for {CPU,DDR}_PLL on AR934x
  MIPS: BCM63XX: Properly handle mac address octet overflow
  MIPS: Kconfig: Avoid build errors by hiding USE_OF from the user.
  MIPS: Replace `-' in defconfig filename wth `_' for consistency.
  MIPS: Wire kcmp syscall.
  MIPS: MIPSsim: Remove the MIPSsim platform.
  MIPS: NOTIFY_RESUME is not needed in TIF masks
  MIPS: Merge the identical "return from syscall" per-ABI code
  MIPS: Unobfuscate _TIF..._MASK
  MIPS: Prevent hitting do_notify_resume() with !user_mode(regs).
  MIPS: Replace 'kernel_uses_smartmips_rixi' with 'cpu_has_rixi'.
  MIPS: Add base architecture support for RI and XI.
  MIPS: Optimise TLB handlers for MIPS32/64 R2 cores.
  MIPS: uasm: Add INS and EXT instructions.
  MIPS: Avoid pipeline stalls on some MIPS32R2 cores.
  MIPS: Make VPE count to be one-based.
  MIPS: Add new end of interrupt functionality for GIC.
  MIPS: Add EIC support for GIC.
  MIPS: Code clean-ups for the GIC.
  ...
parents 50e0d102 382fc33b

Documentation/devicetree/bindings/pinctrl/lantiq,falcon-pinumx.txt

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Lantiq FALCON pinmux controller



Required properties:

- compatible: "lantiq,pinctrl-falcon"

- reg: Should contain the physical address and length of the gpio/pinmux

  register range



Please refer to pinctrl-bindings.txt in this directory for details of the

common pinctrl bindings used by client devices, including the meaning of the

phrase "pin configuration node".



Lantiq's pin configuration nodes act as a container for an abitrary number of

subnodes. Each of these subnodes represents some desired configuration for a

pin, a group, or a list of pins or groups. This configuration can include the

mux function to select on those group(s), and two pin configuration parameters:

pull-up and open-drain



The name of each subnode is not important as long as it is unique; all subnodes

should be enumerated and processed purely based on their content.



Each subnode only affects those parameters that are explicitly listed. In

other words, a subnode that lists a mux function but no pin configuration

parameters implies no information about any pin configuration parameters.

Similarly, a pin subnode that describes a pullup parameter implies no

information about e.g. the mux function.



We support 2 types of nodes.



Definition of mux function groups:



Required subnode-properties:

- lantiq,groups : An array of strings. Each string contains the name of a group.

  Valid values for these names are listed below.

- lantiq,function: A string containing the name of the function to mux to the

  group. Valid values for function names are listed below.



Valid values for group and function names:



  mux groups:

    por, ntr, ntr8k, hrst, mdio, bootled, asc0, spi, spi cs0, spi cs1, i2c,

    jtag, slic, pcm, asc1



  functions:

    rst, ntr, mdio, led, asc, spi, i2c, jtag, slic, pcm





Definition of pin configurations:



Required subnode-properties:

- lantiq,pins : An array of strings. Each string contains the name of a pin.

  Valid values for these names are listed below.



Optional subnode-properties:

- lantiq,pull: Integer, representing the pull-down/up to apply to the pin.

    0: none, 1: down

- lantiq,drive-current: Boolean, enables drive-current

- lantiq,slew-rate: Boolean, enables slew-rate



Example:

	pinmux0 {

		compatible = "lantiq,pinctrl-falcon";

		pinctrl-names = "default";

		pinctrl-0 = <&state_default>;



		state_default: pinmux {

			asc0 {

				lantiq,groups = "asc0";

				lantiq,function = "asc";

			};

			ntr {

				lantiq,groups = "ntr8k";

				lantiq,function = "ntr";

			};

			i2c {

				lantiq,groups = "i2c";

				lantiq,function = "i2c";

			};

			hrst {

				lantiq,groups = "hrst";

				lantiq,function = "rst";

			};

		};

	};

Documentation/devicetree/bindings/pinctrl/lantiq,xway-pinumx.txt

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Lantiq XWAY pinmux controller



Required properties:

- compatible: "lantiq,pinctrl-xway" or "lantiq,pinctrl-xr9"

- reg: Should contain the physical address and length of the gpio/pinmux

  register range



Please refer to pinctrl-bindings.txt in this directory for details of the

common pinctrl bindings used by client devices, including the meaning of the

phrase "pin configuration node".



Lantiq's pin configuration nodes act as a container for an abitrary number of

subnodes. Each of these subnodes represents some desired configuration for a

pin, a group, or a list of pins or groups. This configuration can include the

mux function to select on those group(s), and two pin configuration parameters:

pull-up and open-drain



The name of each subnode is not important as long as it is unique; all subnodes

should be enumerated and processed purely based on their content.



Each subnode only affects those parameters that are explicitly listed. In

other words, a subnode that lists a mux function but no pin configuration

parameters implies no information about any pin configuration parameters.

Similarly, a pin subnode that describes a pullup parameter implies no

information about e.g. the mux function.



We support 2 types of nodes.



Definition of mux function groups:



Required subnode-properties:

- lantiq,groups : An array of strings. Each string contains the name of a group.

  Valid values for these names are listed below.

- lantiq,function: A string containing the name of the function to mux to the

  group. Valid values for function names are listed below.



Valid values for group and function names:



  mux groups:

    exin0, exin1, exin2, jtag, ebu a23, ebu a24, ebu a25, ebu clk, ebu cs1,

    ebu wait, nand ale, nand cs1, nand cle, spi, spi_cs1, spi_cs2, spi_cs3,

    spi_cs4, spi_cs5, spi_cs6, asc0, asc0 cts rts, stp, nmi , gpt1, gpt2,

    gpt3, clkout0, clkout1, clkout2, clkout3, gnt1, gnt2, gnt3, req1, req2,

    req3



  additional mux groups (XR9 only):

    mdio, nand rdy, nand rd, exin3, exin4, gnt4, req4



  functions:

    spi, asc, cgu, jtag, exin, stp, gpt, nmi, pci, ebu, mdio







Definition of pin configurations:



Required subnode-properties:

- lantiq,pins : An array of strings. Each string contains the name of a pin.

  Valid values for these names are listed below.



Optional subnode-properties:

- lantiq,pull: Integer, representing the pull-down/up to apply to the pin.

    0: none, 1: down, 2: up.

- lantiq,open-drain: Boolean, enables open-drain on the defined pin.



Valid values for XWAY pin names:

  Pinconf pins can be referenced via the names io0-io31.



Valid values for XR9 pin names:

  Pinconf pins can be referenced via the names io0-io55.



Example:

	gpio: pinmux@E100B10 {

		compatible = "lantiq,pinctrl-xway";

		pinctrl-names = "default";

		pinctrl-0 = <&state_default>;



		#gpio-cells = <2>;

		gpio-controller;

		reg = <0xE100B10 0xA0>;



		state_default: pinmux {

			stp {

				lantiq,groups = "stp";

				lantiq,function = "stp";

			};

			pci {

				lantiq,groups = "gnt1";

				lantiq,function = "pci";

			};

			conf_out {

				lantiq,pins = "io4", "io5", "io6"; /* stp */

				lantiq,open-drain;

				lantiq,pull = <0>;

			};

		};

	};

Documentation/devicetree/bindings/spi/spi-octeon.txt

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Cavium, Inc. OCTEON SOC SPI master controller.



Required properties:

- compatible : "cavium,octeon-3010-spi"

- reg : The register base for the controller.

- interrupts : One interrupt, used by the controller.

- #address-cells : <1>, as required by generic SPI binding.

- #size-cells : <0>, also as required by generic SPI binding.



Child nodes as per the generic SPI binding.



Example:



	spi@1070000001000 {

		compatible = "cavium,octeon-3010-spi";

		reg = <0x10700 0x00001000 0x0 0x100>;

		interrupts = <0 58>;

		#address-cells = <1>;

		#size-cells = <0>;



		eeprom@0 {

			compatible = "st,m95256", "atmel,at25";

			reg = <0>;

			spi-max-frequency = <5000000>;

			spi-cpha;

			spi-cpol;



			pagesize = <64>;

			size = <32768>;

			address-width = <16>;

		};

	};

arch/mips/Kbuild.platforms

+1 −1
Original line number Diff line number Diff line
@@ -15,8 +15,8 @@ platforms += lantiq 
platforms += lasat

platforms += loongson

platforms += loongson1

platforms += mipssim

platforms += mti-malta

platforms += mti-sead3

platforms += netlogic

platforms += pmc-sierra

platforms += pnx833x

arch/mips/Kconfig

+34 −12
Original line number Diff line number Diff line
@@ -242,6 +242,8 @@ config LANTIQ 
	select HAVE_MACH_CLKDEV

	select CLKDEV_LOOKUP

	select USE_OF

	select PINCTRL

	select PINCTRL_LANTIQ



config LASAT

	bool "LASAT Networks platforms"
@@ -320,24 +322,35 @@ config MIPS_MALTA 
	  This enables support for the MIPS Technologies Malta evaluation

	  board.



config MIPS_SIM

	bool 'MIPS simulator (MIPSsim)'

config MIPS_SEAD3

	bool "MIPS SEAD3 board"

	select BOOT_ELF32

	select BOOT_RAW

	select CEVT_R4K

	select CSRC_R4K

	select CPU_MIPSR2_IRQ_VI

	select CPU_MIPSR2_IRQ_EI

	select DMA_NONCOHERENT

	select SYS_HAS_EARLY_PRINTK

	select IRQ_CPU

	select BOOT_RAW

	select IRQ_GIC

	select MIPS_BOARDS_GEN

	select MIPS_CPU_SCACHE

	select MIPS_MSC

	select SYS_HAS_CPU_MIPS32_R1

	select SYS_HAS_CPU_MIPS32_R2

	select SYS_HAS_CPU_MIPS64_R1

	select SYS_HAS_EARLY_PRINTK

	select SYS_SUPPORTS_32BIT_KERNEL

	select SYS_SUPPORTS_64BIT_KERNEL

	select SYS_SUPPORTS_BIG_ENDIAN

	select SYS_SUPPORTS_MULTITHREADING

	select SYS_SUPPORTS_LITTLE_ENDIAN

	select SYS_SUPPORTS_SMARTMIPS

	select USB_ARCH_HAS_EHCI

	select USB_EHCI_BIG_ENDIAN_DESC

	select USB_EHCI_BIG_ENDIAN_MMIO

	help

	  This option enables support for MIPS Technologies MIPSsim software

	  emulator.

	  This enables support for the MIPS Technologies SEAD3 evaluation

	  board.



config NEC_MARKEINS

	bool "NEC EMMA2RH Mark-eins board"
@@ -831,6 +844,7 @@ config NLM_XLP_BOARD 
	select ZONE_DMA if 64BIT

	select SYNC_R4K

	select SYS_HAS_EARLY_PRINTK

	select USE_OF

	help

	  This board is based on Netlogic XLP Processor.

	  Say Y here if you have a XLP based board.
@@ -1749,7 +1763,6 @@ config HARDWARE_WATCHPOINTS 
menu "Kernel type"



choice



	prompt "Kernel code model"

	help

	  You should only select this option if you have a workload that
@@ -1880,6 +1893,18 @@ config SIBYTE_DMA_PAGEOPS 
config CPU_HAS_PREFETCH

	bool



config CPU_GENERIC_DUMP_TLB

	bool

	default y if !(CPU_R3000 || CPU_R6000 || CPU_R8000 || CPU_TX39XX)



config CPU_R4K_FPU

	bool

	default y if !(CPU_R3000 || CPU_R6000 || CPU_TX39XX || CPU_CAVIUM_OCTEON)



config CPU_R4K_CACHE_TLB

	bool

	default y if !(CPU_R3000 || CPU_R8000 || CPU_SB1 || CPU_TX39XX || CPU_CAVIUM_OCTEON)



choice

	prompt "MIPS MT options"
@@ -1955,7 +1980,6 @@ config SCHED_SMT 
config SYS_SUPPORTS_SCHED_SMT

	bool





config SYS_SUPPORTS_MULTITHREADING

	bool
@@ -2360,12 +2384,10 @@ config SECCOMP 
	  If unsure, say Y. Only embedded should say N here.



config USE_OF

	bool "Flattened Device Tree support"

	bool

	select OF

	select OF_EARLY_FLATTREE

	select IRQ_DOMAIN

	help

	  Include support for flattened device tree machine descriptions.



endmenu

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