Commit de1ca2d0 authored by Jerome Brunet's avatar Jerome Brunet
Browse files

clk: meson: axg: let mpll clocks round closest 



Let the mpll dividers achieve the closest rate possible, even if
it means rounding the requested rate up.

This is done to improve the accuracy of the rates provided by these
plls to the audio subsystem

Acked-by: default avatarNeil Armstrong <narmstrong@baylibre.com>
Signed-off-by: default avatarJerome Brunet <jbrunet@baylibre.com>
parent bae1106c

drivers/clk/meson/axg.c

+4 −0
Original line number Diff line number Diff line
@@ -461,6 +461,7 @@ static struct clk_regmap axg_mpll0_div = { 
			.width	 = 1,

		},

		.lock = &meson_clk_lock,

		.flags = CLK_MESON_MPLL_ROUND_CLOSEST,

	},

	.hw.init = &(struct clk_init_data){

		.name = "mpll0_div",
@@ -507,6 +508,7 @@ static struct clk_regmap axg_mpll1_div = { 
			.width	 = 1,

		},

		.lock = &meson_clk_lock,

		.flags = CLK_MESON_MPLL_ROUND_CLOSEST,

	},

	.hw.init = &(struct clk_init_data){

		.name = "mpll1_div",
@@ -553,6 +555,7 @@ static struct clk_regmap axg_mpll2_div = { 
			.width	 = 1,

		},

		.lock = &meson_clk_lock,

		.flags = CLK_MESON_MPLL_ROUND_CLOSEST,

	},

	.hw.init = &(struct clk_init_data){

		.name = "mpll2_div",
@@ -599,6 +602,7 @@ static struct clk_regmap axg_mpll3_div = { 
			.width	 = 1,

		},

		.lock = &meson_clk_lock,

		.flags = CLK_MESON_MPLL_ROUND_CLOSEST,

	},

	.hw.init = &(struct clk_init_data){

		.name = "mpll3_div",

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