Commit de17a378 authored by Christoph Hellwig's avatar Christoph Hellwig Committed by Borislav Petkov
Browse files

x86/mm: Unexport __cachemode2pte_tbl 



Exporting the raw data for a table is generally a bad idea. Move
cachemode2protval() out of line given that it isn't really used in the
fast path, and then mark __cachemode2pte_tbl static.

Signed-off-by: default avatarChristoph Hellwig <hch@lst.de>
Signed-off-by: default avatarBorislav Petkov <bp@suse.de>
Acked-by: default avatarPeter Zijlstra (Intel) <peterz@infradead.org>
Link: https://lkml.kernel.org/r/20200408152745.1565832-5-hch@lst.de
parent d0735693

arch/x86/include/asm/pgtable_types.h

+2 −12
Original line number Diff line number Diff line
@@ -467,8 +467,6 @@ static inline pteval_t pte_flags(pte_t pte) 
	return native_pte_val(pte) & PTE_FLAGS_MASK;

}



extern uint16_t __cachemode2pte_tbl[_PAGE_CACHE_MODE_NUM];



#define __pte2cm_idx(cb)				\

	((((cb) >> (_PAGE_BIT_PAT - 2)) & 4) |		\

	 (((cb) >> (_PAGE_BIT_PCD - 1)) & 2) |		\
@@ -478,16 +476,8 @@ extern uint16_t __cachemode2pte_tbl[_PAGE_CACHE_MODE_NUM]; 
	 (((i) & 2) << (_PAGE_BIT_PCD - 1)) |		\

	 (((i) & 1) << _PAGE_BIT_PWT))



static inline unsigned long cachemode2protval(enum page_cache_mode pcm)

{

	if (likely(pcm == 0))

		return 0;

	return __cachemode2pte_tbl[pcm];

}

static inline pgprot_t cachemode2pgprot(enum page_cache_mode pcm)

{

	return __pgprot(cachemode2protval(pcm));

}

unsigned long cachemode2protval(enum page_cache_mode pcm);



static inline unsigned long protval_4k_2_large(unsigned long val)

{

	return (val & ~(_PAGE_PAT | _PAGE_PAT_LARGE)) |

arch/x86/mm/init.c

+9 −2
Original line number Diff line number Diff line
@@ -49,7 +49,7 @@ 
 *   Index into __pte2cachemode_tbl[] are the caching attribute bits of the pte

 *   (_PAGE_PWT, _PAGE_PCD, _PAGE_PAT) at index bit positions 0, 1, 2.

 */

uint16_t __cachemode2pte_tbl[_PAGE_CACHE_MODE_NUM] = {

static uint16_t __cachemode2pte_tbl[_PAGE_CACHE_MODE_NUM] = {

	[_PAGE_CACHE_MODE_WB      ]	= 0         | 0        ,

	[_PAGE_CACHE_MODE_WC      ]	= 0         | _PAGE_PCD,

	[_PAGE_CACHE_MODE_UC_MINUS]	= 0         | _PAGE_PCD,
@@ -57,7 +57,14 @@ uint16_t __cachemode2pte_tbl[_PAGE_CACHE_MODE_NUM] = { 
	[_PAGE_CACHE_MODE_WT      ]	= 0         | _PAGE_PCD,

	[_PAGE_CACHE_MODE_WP      ]	= 0         | _PAGE_PCD,

};

EXPORT_SYMBOL(__cachemode2pte_tbl);



unsigned long cachemode2protval(enum page_cache_mode pcm)

{

	if (likely(pcm == 0))

		return 0;

	return __cachemode2pte_tbl[pcm];

}

EXPORT_SYMBOL(cachemode2protval);



static uint8_t __pte2cachemode_tbl[8] = {

	[__pte2cm_idx( 0        | 0         | 0        )] = _PAGE_CACHE_MODE_WB,

arch/x86/mm/pat/set_memory.c

+5 −0
Original line number Diff line number Diff line
@@ -68,6 +68,11 @@ static DEFINE_SPINLOCK(cpa_lock); 
#define CPA_PAGES_ARRAY 4

#define CPA_NO_CHECK_ALIAS 8 /* Do not search for aliases */



static inline pgprot_t cachemode2pgprot(enum page_cache_mode pcm)

{

	return __pgprot(cachemode2protval(pcm));

}



#ifdef CONFIG_PROC_FS

static unsigned long direct_pages_count[PG_LEVEL_NUM];

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