ALSA: hda - add more ML register definitions (dde5bff5) · Commits · 戴 / test

include/sound/hda_register.h

+5 −3

Original line number	Original line	Diff line number	Diff line
	@@ -261,9 +261,11 @@ enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
	#define AZX_REG_ML_LOUTPAY 0x20		#define AZX_REG_ML_LOUTPAY 0x20
	#define AZX_REG_ML_LINPAY 0x30		#define AZX_REG_ML_LINPAY 0x30

	#define AZX_MLCTL_SPA (1<<16)		#define ML_LCTL_SCF_MASK 0xF
	#define AZX_MLCTL_CPA 23		#define AZX_MLCTL_SPA (0x1 << 16)
			#define AZX_MLCTL_CPA (0x1 << 23)
			#define AZX_MLCTL_SPA_SHIFT 16
			#define AZX_MLCTL_CPA_SHIFT 23

	/* registers for DMA Resume Capability Structure */		/* registers for DMA Resume Capability Structure */
	#define AZX_DRSM_CAP_ID 0x5		#define AZX_DRSM_CAP_ID 0x5

+3 −3

Original line number	Original line	Diff line number	Diff line
	@@ -171,7 +171,7 @@ static int check_hdac_link_power_active(struct hdac_ext_link *link, bool enable)
	{		{
	int timeout;		int timeout;
	u32 val;		u32 val;
	int mask = (1 << AZX_MLCTL_CPA);		int mask = (1 << AZX_MLCTL_CPA_SHIFT);

	udelay(3);		udelay(3);
	timeout = 150;		timeout = 150;
	@@ -179,10 +179,10 @@ static int check_hdac_link_power_active(struct hdac_ext_link *link, bool enable)
	do {		do {
	val = readl(link->ml_addr + AZX_REG_ML_LCTL);		val = readl(link->ml_addr + AZX_REG_ML_LCTL);
	if (enable) {		if (enable) {
	if (((val & mask) >> AZX_MLCTL_CPA))		if (((val & mask) >> AZX_MLCTL_CPA_SHIFT))
	return 0;		return 0;
	} else {		} else {
	if (!((val & mask) >> AZX_MLCTL_CPA))		if (!((val & mask) >> AZX_MLCTL_CPA_SHIFT))
	return 0;		return 0;
	}		}
	udelay(3);		udelay(3);