Commit dd360393 authored by Kirill A. Shutemov's avatar Kirill A. Shutemov Committed by H. Peter Anvin
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x86, cpu: Detect more TLB configuration 



The Intel Software Developer’s Manual covers few more TLB
configurations exposed as CPUID 2 descriptors:

61H Instruction TLB: 4 KByte pages, fully associative, 48 entries
63H Data TLB: 1 GByte pages, 4-way set associative, 4 entries
76H Instruction TLB: 2M/4M pages, fully associative, 8 entries
B5H Instruction TLB: 4KByte pages, 8-way set associative, 64 entries
B6H Instruction TLB: 4KByte pages, 8-way set associative, 128 entries
C1H Shared 2nd-Level TLB: 4 KByte/2MByte pages, 8-way associative, 1024 entries
C2H DTLB DTLB: 2 MByte/$MByte pages, 4-way associative, 16 entries

Let's detect them as well.

Signed-off-by: default avatarKirill A. Shutemov <kirill.shutemov@linux.intel.com>
Link: http://lkml.kernel.org/r/1387801018-14499-1-git-send-email-kirill.shutemov@linux.intel.com


Signed-off-by: default avatarH. Peter Anvin <hpa@linux.intel.com>
parent 802eee95

arch/x86/include/asm/processor.h

+1 −0
Original line number Diff line number Diff line
@@ -72,6 +72,7 @@ extern u16 __read_mostly tlb_lli_4m[NR_INFO]; 
extern u16 __read_mostly tlb_lld_4k[NR_INFO];

extern u16 __read_mostly tlb_lld_2m[NR_INFO];

extern u16 __read_mostly tlb_lld_4m[NR_INFO];

extern u16 __read_mostly tlb_lld_1g[NR_INFO];

extern s8  __read_mostly tlb_flushall_shift;



/*

arch/x86/kernel/cpu/common.c

+4 −3
Original line number Diff line number Diff line
@@ -472,6 +472,7 @@ u16 __read_mostly tlb_lli_4m[NR_INFO]; 
u16 __read_mostly tlb_lld_4k[NR_INFO];

u16 __read_mostly tlb_lld_2m[NR_INFO];

u16 __read_mostly tlb_lld_4m[NR_INFO];

u16 __read_mostly tlb_lld_1g[NR_INFO];



/*

 * tlb_flushall_shift shows the balance point in replacing cr3 write
@@ -486,13 +487,13 @@ void cpu_detect_tlb(struct cpuinfo_x86 *c) 
	if (this_cpu->c_detect_tlb)

		this_cpu->c_detect_tlb(c);



	printk(KERN_INFO "Last level iTLB entries: 4KB %d, 2MB %d, 4MB %d\n" \

		"Last level dTLB entries: 4KB %d, 2MB %d, 4MB %d\n"	     \

	printk(KERN_INFO "Last level iTLB entries: 4KB %d, 2MB %d, 4MB %d\n"

		"Last level dTLB entries: 4KB %d, 2MB %d, 4MB %d, 1GB %d\n"

		"tlb_flushall_shift: %d\n",

		tlb_lli_4k[ENTRIES], tlb_lli_2m[ENTRIES],

		tlb_lli_4m[ENTRIES], tlb_lld_4k[ENTRIES],

		tlb_lld_2m[ENTRIES], tlb_lld_4m[ENTRIES],

		tlb_flushall_shift);

		tlb_lld_1g[ENTRIES], tlb_flushall_shift);

}



void detect_ht(struct cpuinfo_x86 *c)

arch/x86/kernel/cpu/intel.c

+26 −0
Original line number Diff line number Diff line
@@ -506,6 +506,7 @@ static unsigned int intel_size_cache(struct cpuinfo_x86 *c, unsigned int size) 
#define TLB_DATA0_2M_4M	0x23



#define STLB_4K		0x41

#define STLB_4K_2M	0x42



static const struct _tlb_table intel_tlb_table[] = {

	{ 0x01, TLB_INST_4K,		32,	" TLB_INST 4 KByte pages, 4-way set associative" },
@@ -526,13 +527,20 @@ static const struct _tlb_table intel_tlb_table[] = { 
	{ 0x5b, TLB_DATA_4K_4M,		64,	" TLB_DATA 4 KByte and 4 MByte pages" },

	{ 0x5c, TLB_DATA_4K_4M,		128,	" TLB_DATA 4 KByte and 4 MByte pages" },

	{ 0x5d, TLB_DATA_4K_4M,		256,	" TLB_DATA 4 KByte and 4 MByte pages" },

	{ 0x61, TLB_INST_4K,		48,	" TLB_INST 4 KByte pages, full associative" },

	{ 0x63, TLB_DATA_1G,		4,	" TLB_DATA 1 GByte pages, 4-way set associative" },

	{ 0x76, TLB_INST_2M_4M,		8,	" TLB_INST 2-MByte or 4-MByte pages, fully associative" },

	{ 0xb0, TLB_INST_4K,		128,	" TLB_INST 4 KByte pages, 4-way set associative" },

	{ 0xb1, TLB_INST_2M_4M,		4,	" TLB_INST 2M pages, 4-way, 8 entries or 4M pages, 4-way entries" },

	{ 0xb2, TLB_INST_4K,		64,	" TLB_INST 4KByte pages, 4-way set associative" },

	{ 0xb3, TLB_DATA_4K,		128,	" TLB_DATA 4 KByte pages, 4-way set associative" },

	{ 0xb4, TLB_DATA_4K,		256,	" TLB_DATA 4 KByte pages, 4-way associative" },

	{ 0xb5, TLB_INST_4K,		64,	" TLB_INST 4 KByte pages, 8-way set ssociative" },

	{ 0xb6, TLB_INST_4K,		128,	" TLB_INST 4 KByte pages, 8-way set ssociative" },

	{ 0xba, TLB_DATA_4K,		64,	" TLB_DATA 4 KByte pages, 4-way associative" },

	{ 0xc0, TLB_DATA_4K_4M,		8,	" TLB_DATA 4 KByte and 4 MByte pages, 4-way associative" },

	{ 0xc1, STLB_4K_2M,		1024,	" STLB 4 KByte and 2 MByte pages, 8-way associative" },

	{ 0xc2, TLB_DATA_2M_4M,		16,	" DTLB 2 MByte/4MByte pages, 4-way associative" },

	{ 0xca, STLB_4K,		512,	" STLB 4 KByte pages, 4-way associative" },

	{ 0x00, 0, 0 }

};
@@ -558,6 +566,20 @@ static void intel_tlb_lookup(const unsigned char desc) 
		if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries)

			tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries;

		break;

	case STLB_4K_2M:

		if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries)

			tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries;

		if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries)

			tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries;

		if (tlb_lli_2m[ENTRIES] < intel_tlb_table[k].entries)

			tlb_lli_2m[ENTRIES] = intel_tlb_table[k].entries;

		if (tlb_lld_2m[ENTRIES] < intel_tlb_table[k].entries)

			tlb_lld_2m[ENTRIES] = intel_tlb_table[k].entries;

		if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries)

			tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries;

		if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries)

			tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries;

		break;

	case TLB_INST_ALL:

		if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries)

			tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries;
@@ -603,6 +625,10 @@ static void intel_tlb_lookup(const unsigned char desc) 
		if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries)

			tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries;

		break;

	case TLB_DATA_1G:

		if (tlb_lld_1g[ENTRIES] < intel_tlb_table[k].entries)

			tlb_lld_1g[ENTRIES] = intel_tlb_table[k].entries;

		break;

	}

}

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