Commit dd0bc75e authored by Ralf Baechle's avatar Ralf Baechle
Browse files

MIPS: SB1: Remove support for Pass 1 parts. 



Pass 1 parts had a number of significant erratas and were only available
in small numbers and under NDA.  Full support also required the use of a
special toolchain that kept branches properly aligned.  These workarounds
were never upstreamed and the only toolchain known to have them is
Montavista's GCC 3.0-based toolchain which completly obsoleted if not
useless these days.

So now that automated testing has tripped over the user of the
-msb1-pass1-workarounds option, rather than fixing it remove support for
pass 1 parts.

Probably nobody will notice.  I seem to own the last know pass 1 board
and I haven't noticed another one in the wild in the past decade, at
least.

Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent 4e9d324d

arch/mips/Kconfig

+0 −5
Original line number Diff line number Diff line
@@ -2263,11 +2263,6 @@ config MIPS_CM 
config MIPS_CPC

	bool



config SB1_PASS_1_WORKAROUNDS

	bool

	depends on CPU_SB1_PASS_1

	default y



config SB1_PASS_2_WORKAROUNDS

	bool

	depends on CPU_SB1 && (CPU_SB1_PASS_2_2 || CPU_SB1_PASS_2)

arch/mips/Makefile

+0 −7
Original line number Diff line number Diff line
@@ -181,13 +181,6 @@ cflags-$(CONFIG_CPU_R4000_WORKAROUNDS) += $(call cc-option,-mfix-r4000,) 
cflags-$(CONFIG_CPU_R4400_WORKAROUNDS)	+= $(call cc-option,-mfix-r4400,)

cflags-$(CONFIG_CPU_DADDI_WORKAROUNDS)	+= $(call cc-option,-mno-daddi,)



ifdef CONFIG_CPU_SB1

ifdef CONFIG_SB1_PASS_1_WORKAROUNDS

KBUILD_AFLAGS_MODULE += -msb1-pass1-workarounds

KBUILD_CFLAGS_MODULE += -msb1-pass1-workarounds

endif

endif



# For smartmips configurations, there are hundreds of warnings due to ISA overrides

# in assembly and header files. smartmips is only supported for MIPS32r1 onwards

# and there is no support for 64-bit. Various '.set mips2' or '.set mips3' or

arch/mips/include/asm/mach-sibyte/war.h

+1 −2
Original line number Diff line number Diff line
@@ -13,8 +13,7 @@ 
#define R4600_V2_HIT_CACHEOP_WAR	0

#define R5432_CP0_INTERRUPT_WAR		0



#if defined(CONFIG_SB1_PASS_1_WORKAROUNDS) || \

    defined(CONFIG_SB1_PASS_2_WORKAROUNDS)

#if defined(CONFIG_SB1_PASS_2_WORKAROUNDS)



#ifndef __ASSEMBLY__

extern int sb1250_m3_workaround_needed(void);

arch/mips/sibyte/Kconfig

+0 −5
Original line number Diff line number Diff line
@@ -81,11 +81,6 @@ choice 
	prompt "SiByte SOC Stepping"

	depends on SIBYTE_SB1xxx_SOC



config CPU_SB1_PASS_1

	bool "1250 Pass1"

	depends on SIBYTE_SB1250

	select CPU_HAS_PREFETCH



config CPU_SB1_PASS_2_1250

	bool "1250 An"

	depends on SIBYTE_SB1250

arch/mips/sibyte/common/bus_watcher.c

+1 −4
Original line number Diff line number Diff line
@@ -81,10 +81,7 @@ void check_bus_watcher(void) 
{

	u32 status, l2_err, memio_err;



#ifdef CONFIG_SB1_PASS_1_WORKAROUNDS

	/* Destructive read, clears register and interrupt */

	status = csr_in32(IOADDR(A_SCD_BUS_ERR_STATUS));

#elif defined(CONFIG_SIBYTE_BCM112X) || defined(CONFIG_SIBYTE_SB1250)

#if defined(CONFIG_SIBYTE_BCM112X) || defined(CONFIG_SIBYTE_SB1250)

	/* Use non-destructive register */

	status = csr_in32(IOADDR(A_SCD_BUS_ERR_STATUS_DEBUG));

#elif defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80)

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