Commit dcded10f authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/djbw/async_tx 

* 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/djbw/async_tx: (30 commits)
  DMAENGINE: at_hdmac: locking fixlet
  DMAENGINE: pch_dma: kill another usage of __raw_{read|write}l
  dma: dmatest: fix potential sign bug
  ioat2: catch and recover from broken vtd configurations v6
  DMAENGINE: add runtime slave control to COH 901 318 v3
  DMAENGINE: add runtime slave config to DMA40 v3
  DMAENGINE: generic slave channel control v3
  dmaengine: Driver for Topcliff PCH DMA controller
  intel_mid: Add Mrst & Mfld DMA Drivers
  drivers/dma: Eliminate a NULL pointer dereference
  dma/timb_dma: compile warning on 32 bit
  DMAENGINE: ste_dma40: support older silicon
  DMAENGINE: ste_dma40: support disabling physical channels
  DMAENGINE: ste_dma40: no disabled phy channels on ux500
  DMAENGINE: ste_dma40: fix suspend bug
  DMAENGINE: ste_dma40: add DB8500 memcpy channels
  DMAENGINE: ste_dma40: no flow control on memcpy
  DMAENGINE: ste_dma40: arch updates for LCLA and LCPA
  DMAENGINE: ste_dma40: allocate LCLA dynamically
  DMAENGINE: ste_dma40: no premature stop
  ...

Fix up trivial conflicts in arch/arm/mach-ux500/devices-db8500.c
parents 9e0ba741 b0ebeb9c

arch/arm/mach-ux500/devices-db8500.c

+15 −13
Original line number Diff line number Diff line
@@ -119,20 +119,15 @@ static struct resource dma40_resources[] = { 
	},

	[1] = {

		.start = U8500_DMA_LCPA_BASE,

		.end = U8500_DMA_LCPA_BASE + SZ_4K - 1,

		.end   = U8500_DMA_LCPA_BASE + 2 * SZ_1K - 1,

		.flags = IORESOURCE_MEM,

		.name  = "lcpa",

	},

	[2] = {

		.start = U8500_DMA_LCLA_BASE,

		.end = U8500_DMA_LCLA_BASE + 16 * 1024 - 1,

		.flags = IORESOURCE_MEM,

		.name = "lcla",

	},

	[3] = {

		.start = IRQ_DB8500_DMA,

		.end   = IRQ_DB8500_DMA,

		.flags = IORESOURCE_IRQ}

		.flags = IORESOURCE_IRQ,

	}

};



/* Default configuration for physcial memcpy */
@@ -145,11 +140,12 @@ struct stedma40_chan_cfg dma40_memcpy_conf_phy = { 
	.src_info.endianess = STEDMA40_LITTLE_ENDIAN,

	.src_info.data_width = STEDMA40_BYTE_WIDTH,

	.src_info.psize = STEDMA40_PSIZE_PHY_1,

	.src_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL,



	.dst_info.endianess = STEDMA40_LITTLE_ENDIAN,

	.dst_info.data_width = STEDMA40_BYTE_WIDTH,

	.dst_info.psize = STEDMA40_PSIZE_PHY_1,



	.dst_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL,

};

/* Default configuration for logical memcpy */

struct stedma40_chan_cfg dma40_memcpy_conf_log = {
@@ -162,11 +158,12 @@ struct stedma40_chan_cfg dma40_memcpy_conf_log = { 
	.src_info.endianess = STEDMA40_LITTLE_ENDIAN,

	.src_info.data_width = STEDMA40_BYTE_WIDTH,

	.src_info.psize = STEDMA40_PSIZE_LOG_1,

	.src_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL,



	.dst_info.endianess = STEDMA40_LITTLE_ENDIAN,

	.dst_info.data_width = STEDMA40_BYTE_WIDTH,

	.dst_info.psize = STEDMA40_PSIZE_LOG_1,



	.dst_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL,

};



/*
@@ -180,10 +177,12 @@ static const dma_addr_t dma40_rx_map[STEDMA40_NR_DEV]; 


/* Reserved event lines for memcpy only */

static int dma40_memcpy_event[] = {

	STEDMA40_MEMCPY_TX_0,

	STEDMA40_MEMCPY_TX_1,

	STEDMA40_MEMCPY_TX_2,

	STEDMA40_MEMCPY_TX_3,

	STEDMA40_MEMCPY_TX_4,

	STEDMA40_MEMCPY_TX_5,

};



static struct stedma40_platform_data dma40_plat_data = {
@@ -195,6 +194,7 @@ static struct stedma40_platform_data dma40_plat_data = { 
	.memcpy_conf_phy = &dma40_memcpy_conf_phy,

	.memcpy_conf_log = &dma40_memcpy_conf_log,

	.llis_per_log = 8,

	.disabled_channels = {-1},

};



struct platform_device u8500_dma40_device = {
@@ -213,4 +213,6 @@ void dma40_u8500ed_fixup(void) 
	dma40_plat_data.memcpy_len = 0;

	dma40_resources[0].start = U8500_DMA_BASE_ED;

	dma40_resources[0].end = U8500_DMA_BASE_ED + SZ_4K - 1;

	dma40_resources[1].start = U8500_DMA_LCPA_BASE_ED;

	dma40_resources[1].end = U8500_DMA_LCPA_BASE_ED + 2 * SZ_1K - 1;

}

arch/arm/mach-ux500/include/mach/db8500-regs.h

+3 −3
Original line number Diff line number Diff line
@@ -15,9 +15,9 @@ 
#define U8500_ESRAM_BANK2	(U8500_ESRAM_BANK1 + U8500_ESRAM_BANK_SIZE)

#define U8500_ESRAM_BANK3	(U8500_ESRAM_BANK2 + U8500_ESRAM_BANK_SIZE)

#define U8500_ESRAM_BANK4	(U8500_ESRAM_BANK3 + U8500_ESRAM_BANK_SIZE)

/* Use bank 4 for DMA LCLA and LCPA */

#define U8500_DMA_LCLA_BASE	U8500_ESRAM_BANK4

#define U8500_DMA_LCPA_BASE	(U8500_ESRAM_BANK4 + 0x4000)

/* Use bank 4 for DMA LCPA */

#define U8500_DMA_LCPA_BASE	U8500_ESRAM_BANK4

#define U8500_DMA_LCPA_BASE_ED	(U8500_ESRAM_BANK4 + 0x4000)



#define U8500_PER3_BASE		0x80000000

#define U8500_STM_BASE		0x80100000

arch/arm/mach-ux500/ste-dma40-db8500.h

+1 −1
Original line number Diff line number Diff line
@@ -136,7 +136,7 @@ enum dma_dest_dev_type { 
	STEDMA40_DEV_CAC1_TX = 48,

	STEDMA40_DEV_CAC1_TX_HAC1_TX = 49,

	STEDMA40_DEV_HAC1_TX = 50,

	STEDMA40_MEMXCPY_TX_0 = 51,

	STEDMA40_MEMCPY_TX_0 = 51,

	STEDMA40_DEV_SLIM1_CH0_TX_HSI_TX_CH4 = 52,

	STEDMA40_DEV_SLIM1_CH1_TX_HSI_TX_CH5 = 53,

	STEDMA40_DEV_SLIM1_CH2_TX_HSI_TX_CH6 = 54,

arch/arm/plat-nomadik/include/plat/ste_dma40.h

+3 −1
Original line number Diff line number Diff line
@@ -148,7 +148,8 @@ struct stedma40_chan_cfg { 
 * @memcpy_conf_phy: default configuration of physical channel memcpy

 * @memcpy_conf_log: default configuration of logical channel memcpy

 * @llis_per_log: number of max linked list items per logical channel

 *

 * @disabled_channels: A vector, ending with -1, that marks physical channels

 * that are for different reasons not available for the driver.

 */

struct stedma40_platform_data {

	u32				 dev_len;
@@ -159,6 +160,7 @@ struct stedma40_platform_data { 
	struct stedma40_chan_cfg	*memcpy_conf_phy;

	struct stedma40_chan_cfg	*memcpy_conf_log;

	unsigned int			 llis_per_log;

	int				 disabled_channels[8];

};



/**

drivers/dma/Kconfig

+20 −0
Original line number Diff line number Diff line
@@ -33,6 +33,19 @@ if DMADEVICES 


comment "DMA Devices"



config INTEL_MID_DMAC

	tristate "Intel MID DMA support for Peripheral DMA controllers"

	depends on PCI && X86

	select DMA_ENGINE

	default n

	help

	  Enable support for the Intel(R) MID DMA engine present

	  in Intel MID chipsets.



	  Say Y here if you have such a chipset.



	  If unsure, say N.



config ASYNC_TX_DISABLE_CHANNEL_SWITCH

	bool
@@ -175,6 +188,13 @@ config PL330_DMA 
	  You need to provide platform specific settings via

	  platform_data for a dma-pl330 device.



config PCH_DMA

	tristate "Topcliff PCH DMA support"

	depends on PCI && X86

	select DMA_ENGINE

	help

	  Enable support for the Topcliff PCH DMA engine.



config DMA_ENGINE

	bool

CRA Git | Maintained and supported by SUSTech CRA and CCSE