Commit dcdcc660 authored by Kevin Hilman's avatar Kevin Hilman
Browse files

Merge branch 'clk-meson-gxbb' of... 

Merge branch 'clk-meson-gxbb' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux into v4.8/drivers

* 'clk-meson-gxbb' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux:
  clk: meson-gxbb: Export PWM related clocks for DT
  meson: clk: Add support for clock gates
  gxbb: clk: Adjust MESON_GATE macro to be shared with meson8b
  clk: meson: Copy meson8b CLKID defines to private header file
  meson: clk: Rename register names according to Amlogic datasheet
  meson: clk: Move register definitions to meson8b.h
  clk: meson: Rename meson8b-clkc.c to reflect gxbb naming convention
  clk: meson: Fix invalid use of sizeof in gxbb_aoclkc_probe()
  clk: meson: Add GXBB AO Clock and Reset controller driver
  dt-bindings: clock: reset: Add GXBB AO Clock and Reset Bindings
  clk: gxbb: add MMC gate clocks, and expose for DT
parents c940d765 19a2a85d

Documentation/devicetree/bindings/clock/amlogic,gxbb-aoclkc.txt

0 → 100644
+45 −0
Original line number Diff line number Diff line 
* Amlogic GXBB AO Clock and Reset Unit



The Amlogic GXBB AO clock controller generates and supplies clock to various

controllers within the Always-On part of the SoC.



Required Properties:



- compatible: should be "amlogic,gxbb-aoclkc"

- reg: physical base address of the clock controller and length of memory

       mapped region.



- #clock-cells: should be 1.



Each clock is assigned an identifier and client nodes can use this identifier

to specify the clock which they consume. All available clocks are defined as

preprocessor macros in the dt-bindings/clock/gxbb-aoclkc.h header and can be

used in device tree sources.



- #reset-cells: should be 1.



Each reset is assigned an identifier and client nodes can use this identifier

to specify the reset which they consume. All available resets are defined as

preprocessor macros in the dt-bindings/reset/gxbb-aoclkc.h header and can be

used in device tree sources.



Example: AO Clock controller node:



	clkc_AO: clock-controller@040 {

		compatible = "amlogic,gxbb-aoclkc";

		reg = <0x0 0x040 0x0 0x4>;

		#clock-cells = <1>;

		#reset-cells = <1>;

	};



Example: UART controller node that consumes the clock and reset generated

  by the clock controller:



	uart_AO: serial@4c0 {

		compatible = "amlogic,meson-uart";

		reg = <0x4c0 0x14>;

		interrupts = <0 90 1>;

		clocks = <&clkc_AO CLKID_AO_UART1>;

		resets = <&clkc_AO RESET_AO_UART1>;

		status = "disabled";

	};

drivers/clk/meson/Makefile

+2 −2
Original line number Diff line number Diff line
@@ -3,5 +3,5 @@ 
#



obj-$(CONFIG_COMMON_CLK_AMLOGIC) += clk-pll.o clk-cpu.o clk-mpll.o

obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b-clkc.o

obj-$(CONFIG_COMMON_CLK_GXBB)	 += gxbb.o
 
obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o

obj-$(CONFIG_COMMON_CLK_GXBB)	 += gxbb.o gxbb-aoclk.o

drivers/clk/meson/clkc.h

+1 −1
Original line number Diff line number Diff line
@@ -98,7 +98,7 @@ struct meson_clk_mpll { 
};



#define MESON_GATE(_name, _reg, _bit)					\

struct clk_gate gxbb_##_name = { 						\

struct clk_gate _name = { 						\

	.reg = (void __iomem *) _reg, 					\

	.bit_idx = (_bit), 						\

	.lock = &clk_lock,						\

drivers/clk/meson/gxbb-aoclk.c

0 → 100644
+191 −0
Original line number Diff line number Diff line 
/*

 * This file is provided under a dual BSD/GPLv2 license.  When using or

 * redistributing this file, you may do so under either license.

 *

 * GPL LICENSE SUMMARY

 *

 * Copyright (c) 2016 BayLibre, SAS.

 * Author: Neil Armstrong <narmstrong@baylibre.com>

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of version 2 of the GNU General Public License as

 * published by the Free Software Foundation.

 *

 * This program is distributed in the hope that it will be useful, but

 * WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU

 * General Public License for more details.

 *

 * You should have received a copy of the GNU General Public License

 * along with this program; if not, see <http://www.gnu.org/licenses/>.

 * The full GNU General Public License is included in this distribution

 * in the file called COPYING.

 *

 * BSD LICENSE

 *

 * Copyright (c) 2016 BayLibre, SAS.

 * Author: Neil Armstrong <narmstrong@baylibre.com>

 *

 * Redistribution and use in source and binary forms, with or without

 * modification, are permitted provided that the following conditions

 * are met:

 *

 *   * Redistributions of source code must retain the above copyright

 *     notice, this list of conditions and the following disclaimer.

 *   * Redistributions in binary form must reproduce the above copyright

 *     notice, this list of conditions and the following disclaimer in

 *     the documentation and/or other materials provided with the

 *     distribution.

 *   * Neither the name of Intel Corporation nor the names of its

 *     contributors may be used to endorse or promote products derived

 *     from this software without specific prior written permission.

 *

 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS

 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT

 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR

 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT

 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,

 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT

 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,

 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY

 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT

 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE

 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

 */

#include <linux/clk-provider.h>

#include <linux/of_address.h>

#include <linux/platform_device.h>

#include <linux/reset-controller.h>

#include <linux/init.h>

#include <dt-bindings/clock/gxbb-aoclkc.h>

#include <dt-bindings/reset/gxbb-aoclkc.h>



static DEFINE_SPINLOCK(gxbb_aoclk_lock);



struct gxbb_aoclk_reset_controller {

	struct reset_controller_dev reset;

	unsigned int *data;

	void __iomem *base;

};



static int gxbb_aoclk_do_reset(struct reset_controller_dev *rcdev,

			       unsigned long id)

{

	struct gxbb_aoclk_reset_controller *reset =

		container_of(rcdev, struct gxbb_aoclk_reset_controller, reset);



	writel(BIT(reset->data[id]), reset->base);



	return 0;

}



static const struct reset_control_ops gxbb_aoclk_reset_ops = {

	.reset = gxbb_aoclk_do_reset,

};



#define GXBB_AO_GATE(_name, _bit)					\

static struct clk_gate _name##_ao = {					\

	.reg = (void __iomem *)0,					\

	.bit_idx = (_bit),						\

	.lock = &gxbb_aoclk_lock,					\

	.hw.init = &(struct clk_init_data) {				\

		.name = #_name "_ao",					\

		.ops = &clk_gate_ops,					\

		.parent_names = (const char *[]){ "clk81" },		\

		.num_parents = 1,					\

		.flags = (CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED),	\

	},								\

}



GXBB_AO_GATE(remote, 0);

GXBB_AO_GATE(i2c_master, 1);

GXBB_AO_GATE(i2c_slave, 2);

GXBB_AO_GATE(uart1, 3);

GXBB_AO_GATE(uart2, 5);

GXBB_AO_GATE(ir_blaster, 6);



static unsigned int gxbb_aoclk_reset[] = {

	[RESET_AO_REMOTE] = 16,

	[RESET_AO_I2C_MASTER] = 18,

	[RESET_AO_I2C_SLAVE] = 19,

	[RESET_AO_UART1] = 17,

	[RESET_AO_UART2] = 22,

	[RESET_AO_IR_BLASTER] = 23,

};



static struct clk_gate *gxbb_aoclk_gate[] = {

	[CLKID_AO_REMOTE] = &remote_ao,

	[CLKID_AO_I2C_MASTER] = &i2c_master_ao,

	[CLKID_AO_I2C_SLAVE] = &i2c_slave_ao,

	[CLKID_AO_UART1] = &uart1_ao,

	[CLKID_AO_UART2] = &uart2_ao,

	[CLKID_AO_IR_BLASTER] = &ir_blaster_ao,

};



static struct clk_hw_onecell_data gxbb_aoclk_onecell_data = {

	.hws = {

		[CLKID_AO_REMOTE] = &remote_ao.hw,

		[CLKID_AO_I2C_MASTER] = &i2c_master_ao.hw,

		[CLKID_AO_I2C_SLAVE] = &i2c_slave_ao.hw,

		[CLKID_AO_UART1] = &uart1_ao.hw,

		[CLKID_AO_UART2] = &uart2_ao.hw,

		[CLKID_AO_IR_BLASTER] = &ir_blaster_ao.hw,

	},

	.num = ARRAY_SIZE(gxbb_aoclk_gate),

};



static int gxbb_aoclkc_probe(struct platform_device *pdev)

{

	struct resource *res;

	void __iomem *base;

	int ret, clkid;

	struct device *dev = &pdev->dev;

	struct gxbb_aoclk_reset_controller *rstc;



	rstc = devm_kzalloc(dev, sizeof(*rstc), GFP_KERNEL);

	if (!rstc)

		return -ENOMEM;



	/* Generic clocks */

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);

	base = devm_ioremap_resource(dev, res);

	if (IS_ERR(base))

		return PTR_ERR(base);



	/* Reset Controller */

	rstc->base = base;

	rstc->data = gxbb_aoclk_reset;

	rstc->reset.ops = &gxbb_aoclk_reset_ops;

	rstc->reset.nr_resets = ARRAY_SIZE(gxbb_aoclk_reset);

	rstc->reset.of_node = dev->of_node;

	ret = devm_reset_controller_register(dev, &rstc->reset);



	/*

	 * Populate base address and register all clks

	 */

	for (clkid = 0; clkid < gxbb_aoclk_onecell_data.num; clkid++) {

		gxbb_aoclk_gate[clkid]->reg = base;



		ret = devm_clk_hw_register(dev,

					gxbb_aoclk_onecell_data.hws[clkid]);

		if (ret)

			return ret;

	}



	return of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get,

			&gxbb_aoclk_onecell_data);

}



static const struct of_device_id gxbb_aoclkc_match_table[] = {

	{ .compatible = "amlogic,gxbb-aoclkc" },

	{ }

};



static struct platform_driver gxbb_aoclkc_driver = {

	.probe		= gxbb_aoclkc_probe,

	.driver		= {

		.name	= "gxbb-aoclkc",

		.of_match_table = gxbb_aoclkc_match_table,

	},

};

builtin_platform_driver(gxbb_aoclkc_driver);

drivers/clk/meson/gxbb.c

+90 −81
Original line number Diff line number Diff line
@@ -565,90 +565,93 @@ static struct clk_gate gxbb_clk81 = { 
};



/* Everything Else (EE) domain gates */

static MESON_GATE(ddr, HHI_GCLK_MPEG0, 0);

static MESON_GATE(dos, HHI_GCLK_MPEG0, 1);

static MESON_GATE(isa, HHI_GCLK_MPEG0, 5);

static MESON_GATE(pl301, HHI_GCLK_MPEG0, 6);

static MESON_GATE(periphs, HHI_GCLK_MPEG0, 7);

static MESON_GATE(spicc, HHI_GCLK_MPEG0, 8);

static MESON_GATE(i2c, HHI_GCLK_MPEG0, 9);

static MESON_GATE(sar_adc, HHI_GCLK_MPEG0, 10);

static MESON_GATE(smart_card, HHI_GCLK_MPEG0, 11);

static MESON_GATE(rng0, HHI_GCLK_MPEG0, 12);

static MESON_GATE(uart0, HHI_GCLK_MPEG0, 13);

static MESON_GATE(sdhc, HHI_GCLK_MPEG0, 14);

static MESON_GATE(stream, HHI_GCLK_MPEG0, 15);

static MESON_GATE(async_fifo, HHI_GCLK_MPEG0, 16);

static MESON_GATE(sdio, HHI_GCLK_MPEG0, 17);

static MESON_GATE(abuf, HHI_GCLK_MPEG0, 18);

static MESON_GATE(hiu_iface, HHI_GCLK_MPEG0, 19);

static MESON_GATE(assist_misc, HHI_GCLK_MPEG0, 23);

static MESON_GATE(spi, HHI_GCLK_MPEG0, 30);



static MESON_GATE(i2s_spdif, HHI_GCLK_MPEG1, 2);

static MESON_GATE(eth, HHI_GCLK_MPEG1, 3);

static MESON_GATE(demux, HHI_GCLK_MPEG1, 4);

static MESON_GATE(aiu_glue, HHI_GCLK_MPEG1, 6);

static MESON_GATE(iec958, HHI_GCLK_MPEG1, 7);

static MESON_GATE(i2s_out, HHI_GCLK_MPEG1, 8);

static MESON_GATE(amclk, HHI_GCLK_MPEG1, 9);

static MESON_GATE(aififo2, HHI_GCLK_MPEG1, 10);

static MESON_GATE(mixer, HHI_GCLK_MPEG1, 11);

static MESON_GATE(mixer_iface, HHI_GCLK_MPEG1, 12);

static MESON_GATE(adc, HHI_GCLK_MPEG1, 13);

static MESON_GATE(blkmv, HHI_GCLK_MPEG1, 14);

static MESON_GATE(aiu, HHI_GCLK_MPEG1, 15);

static MESON_GATE(uart1, HHI_GCLK_MPEG1, 16);

static MESON_GATE(g2d, HHI_GCLK_MPEG1, 20);

static MESON_GATE(usb0, HHI_GCLK_MPEG1, 21);

static MESON_GATE(usb1, HHI_GCLK_MPEG1, 22);

static MESON_GATE(reset, HHI_GCLK_MPEG1, 23);

static MESON_GATE(nand, HHI_GCLK_MPEG1, 24);

static MESON_GATE(dos_parser, HHI_GCLK_MPEG1, 25);

static MESON_GATE(usb, HHI_GCLK_MPEG1, 26);

static MESON_GATE(vdin1, HHI_GCLK_MPEG1, 28);

static MESON_GATE(ahb_arb0, HHI_GCLK_MPEG1, 29);

static MESON_GATE(efuse, HHI_GCLK_MPEG1, 30);

static MESON_GATE(boot_rom, HHI_GCLK_MPEG1, 31);



static MESON_GATE(ahb_data_bus, HHI_GCLK_MPEG2, 1);

static MESON_GATE(ahb_ctrl_bus, HHI_GCLK_MPEG2, 2);

static MESON_GATE(hdmi_intr_sync, HHI_GCLK_MPEG2, 3);

static MESON_GATE(hdmi_pclk, HHI_GCLK_MPEG2, 4);

static MESON_GATE(usb1_ddr_bridge, HHI_GCLK_MPEG2, 8);

static MESON_GATE(usb0_ddr_bridge, HHI_GCLK_MPEG2, 9);

static MESON_GATE(mmc_pclk, HHI_GCLK_MPEG2, 11);

static MESON_GATE(dvin, HHI_GCLK_MPEG2, 12);

static MESON_GATE(uart2, HHI_GCLK_MPEG2, 15);

static MESON_GATE(sana, HHI_GCLK_MPEG2, 22);

static MESON_GATE(vpu_intr, HHI_GCLK_MPEG2, 25);

static MESON_GATE(sec_ahb_ahb3_bridge, HHI_GCLK_MPEG2, 26);

static MESON_GATE(clk81_a53, HHI_GCLK_MPEG2, 29);



static MESON_GATE(vclk2_venci0, HHI_GCLK_OTHER, 1);

static MESON_GATE(vclk2_venci1, HHI_GCLK_OTHER, 2);

static MESON_GATE(vclk2_vencp0, HHI_GCLK_OTHER, 3);

static MESON_GATE(vclk2_vencp1, HHI_GCLK_OTHER, 4);

static MESON_GATE(gclk_venci_int0, HHI_GCLK_OTHER, 8);

static MESON_GATE(gclk_vencp_int, HHI_GCLK_OTHER, 9);

static MESON_GATE(dac_clk, HHI_GCLK_OTHER, 10);

static MESON_GATE(aoclk_gate, HHI_GCLK_OTHER, 14);

static MESON_GATE(iec958_gate, HHI_GCLK_OTHER, 16);

static MESON_GATE(enc480p, HHI_GCLK_OTHER, 20);

static MESON_GATE(rng1, HHI_GCLK_OTHER, 21);

static MESON_GATE(gclk_venci_int1, HHI_GCLK_OTHER, 22);

static MESON_GATE(vclk2_venclmcc, HHI_GCLK_OTHER, 24);

static MESON_GATE(vclk2_vencl, HHI_GCLK_OTHER, 25);

static MESON_GATE(vclk_other, HHI_GCLK_OTHER, 26);

static MESON_GATE(edp, HHI_GCLK_OTHER, 31);

static MESON_GATE(gxbb_ddr, HHI_GCLK_MPEG0, 0);

static MESON_GATE(gxbb_dos, HHI_GCLK_MPEG0, 1);

static MESON_GATE(gxbb_isa, HHI_GCLK_MPEG0, 5);

static MESON_GATE(gxbb_pl301, HHI_GCLK_MPEG0, 6);

static MESON_GATE(gxbb_periphs, HHI_GCLK_MPEG0, 7);

static MESON_GATE(gxbb_spicc, HHI_GCLK_MPEG0, 8);

static MESON_GATE(gxbb_i2c, HHI_GCLK_MPEG0, 9);

static MESON_GATE(gxbb_sar_adc, HHI_GCLK_MPEG0, 10);

static MESON_GATE(gxbb_smart_card, HHI_GCLK_MPEG0, 11);

static MESON_GATE(gxbb_rng0, HHI_GCLK_MPEG0, 12);

static MESON_GATE(gxbb_uart0, HHI_GCLK_MPEG0, 13);

static MESON_GATE(gxbb_sdhc, HHI_GCLK_MPEG0, 14);

static MESON_GATE(gxbb_stream, HHI_GCLK_MPEG0, 15);

static MESON_GATE(gxbb_async_fifo, HHI_GCLK_MPEG0, 16);

static MESON_GATE(gxbb_sdio, HHI_GCLK_MPEG0, 17);

static MESON_GATE(gxbb_abuf, HHI_GCLK_MPEG0, 18);

static MESON_GATE(gxbb_hiu_iface, HHI_GCLK_MPEG0, 19);

static MESON_GATE(gxbb_assist_misc, HHI_GCLK_MPEG0, 23);

static MESON_GATE(gxbb_emmc_a, HHI_GCLK_MPEG0, 24);

static MESON_GATE(gxbb_emmc_b, HHI_GCLK_MPEG0, 25);

static MESON_GATE(gxbb_emmc_c, HHI_GCLK_MPEG0, 26);

static MESON_GATE(gxbb_spi, HHI_GCLK_MPEG0, 30);



static MESON_GATE(gxbb_i2s_spdif, HHI_GCLK_MPEG1, 2);

static MESON_GATE(gxbb_eth, HHI_GCLK_MPEG1, 3);

static MESON_GATE(gxbb_demux, HHI_GCLK_MPEG1, 4);

static MESON_GATE(gxbb_aiu_glue, HHI_GCLK_MPEG1, 6);

static MESON_GATE(gxbb_iec958, HHI_GCLK_MPEG1, 7);

static MESON_GATE(gxbb_i2s_out, HHI_GCLK_MPEG1, 8);

static MESON_GATE(gxbb_amclk, HHI_GCLK_MPEG1, 9);

static MESON_GATE(gxbb_aififo2, HHI_GCLK_MPEG1, 10);

static MESON_GATE(gxbb_mixer, HHI_GCLK_MPEG1, 11);

static MESON_GATE(gxbb_mixer_iface, HHI_GCLK_MPEG1, 12);

static MESON_GATE(gxbb_adc, HHI_GCLK_MPEG1, 13);

static MESON_GATE(gxbb_blkmv, HHI_GCLK_MPEG1, 14);

static MESON_GATE(gxbb_aiu, HHI_GCLK_MPEG1, 15);

static MESON_GATE(gxbb_uart1, HHI_GCLK_MPEG1, 16);

static MESON_GATE(gxbb_g2d, HHI_GCLK_MPEG1, 20);

static MESON_GATE(gxbb_usb0, HHI_GCLK_MPEG1, 21);

static MESON_GATE(gxbb_usb1, HHI_GCLK_MPEG1, 22);

static MESON_GATE(gxbb_reset, HHI_GCLK_MPEG1, 23);

static MESON_GATE(gxbb_nand, HHI_GCLK_MPEG1, 24);

static MESON_GATE(gxbb_dos_parser, HHI_GCLK_MPEG1, 25);

static MESON_GATE(gxbb_usb, HHI_GCLK_MPEG1, 26);

static MESON_GATE(gxbb_vdin1, HHI_GCLK_MPEG1, 28);

static MESON_GATE(gxbb_ahb_arb0, HHI_GCLK_MPEG1, 29);

static MESON_GATE(gxbb_efuse, HHI_GCLK_MPEG1, 30);

static MESON_GATE(gxbb_boot_rom, HHI_GCLK_MPEG1, 31);



static MESON_GATE(gxbb_ahb_data_bus, HHI_GCLK_MPEG2, 1);

static MESON_GATE(gxbb_ahb_ctrl_bus, HHI_GCLK_MPEG2, 2);

static MESON_GATE(gxbb_hdmi_intr_sync, HHI_GCLK_MPEG2, 3);

static MESON_GATE(gxbb_hdmi_pclk, HHI_GCLK_MPEG2, 4);

static MESON_GATE(gxbb_usb1_ddr_bridge, HHI_GCLK_MPEG2, 8);

static MESON_GATE(gxbb_usb0_ddr_bridge, HHI_GCLK_MPEG2, 9);

static MESON_GATE(gxbb_mmc_pclk, HHI_GCLK_MPEG2, 11);

static MESON_GATE(gxbb_dvin, HHI_GCLK_MPEG2, 12);

static MESON_GATE(gxbb_uart2, HHI_GCLK_MPEG2, 15);

static MESON_GATE(gxbb_sana, HHI_GCLK_MPEG2, 22);

static MESON_GATE(gxbb_vpu_intr, HHI_GCLK_MPEG2, 25);

static MESON_GATE(gxbb_sec_ahb_ahb3_bridge, HHI_GCLK_MPEG2, 26);

static MESON_GATE(gxbb_clk81_a53, HHI_GCLK_MPEG2, 29);



static MESON_GATE(gxbb_vclk2_venci0, HHI_GCLK_OTHER, 1);

static MESON_GATE(gxbb_vclk2_venci1, HHI_GCLK_OTHER, 2);

static MESON_GATE(gxbb_vclk2_vencp0, HHI_GCLK_OTHER, 3);

static MESON_GATE(gxbb_vclk2_vencp1, HHI_GCLK_OTHER, 4);

static MESON_GATE(gxbb_gclk_venci_int0, HHI_GCLK_OTHER, 8);

static MESON_GATE(gxbb_gclk_vencp_int, HHI_GCLK_OTHER, 9);

static MESON_GATE(gxbb_dac_clk, HHI_GCLK_OTHER, 10);

static MESON_GATE(gxbb_aoclk_gate, HHI_GCLK_OTHER, 14);

static MESON_GATE(gxbb_iec958_gate, HHI_GCLK_OTHER, 16);

static MESON_GATE(gxbb_enc480p, HHI_GCLK_OTHER, 20);

static MESON_GATE(gxbb_rng1, HHI_GCLK_OTHER, 21);

static MESON_GATE(gxbb_gclk_venci_int1, HHI_GCLK_OTHER, 22);

static MESON_GATE(gxbb_vclk2_venclmcc, HHI_GCLK_OTHER, 24);

static MESON_GATE(gxbb_vclk2_vencl, HHI_GCLK_OTHER, 25);

static MESON_GATE(gxbb_vclk_other, HHI_GCLK_OTHER, 26);

static MESON_GATE(gxbb_edp, HHI_GCLK_OTHER, 31);



/* Always On (AO) domain gates */



static MESON_GATE(ao_media_cpu, HHI_GCLK_AO, 0);

static MESON_GATE(ao_ahb_sram, HHI_GCLK_AO, 1);

static MESON_GATE(ao_ahb_bus, HHI_GCLK_AO, 2);

static MESON_GATE(ao_iface, HHI_GCLK_AO, 3);

static MESON_GATE(ao_i2c, HHI_GCLK_AO, 4);

static MESON_GATE(gxbb_ao_media_cpu, HHI_GCLK_AO, 0);

static MESON_GATE(gxbb_ao_ahb_sram, HHI_GCLK_AO, 1);

static MESON_GATE(gxbb_ao_ahb_bus, HHI_GCLK_AO, 2);

static MESON_GATE(gxbb_ao_iface, HHI_GCLK_AO, 3);

static MESON_GATE(gxbb_ao_i2c, HHI_GCLK_AO, 4);



/* Array of all clocks provided by this provider */
@@ -748,6 +751,9 @@ static struct clk_hw_onecell_data gxbb_hw_onecell_data = { 
		[CLKID_AO_AHB_BUS]	    = &gxbb_ao_ahb_bus.hw,

		[CLKID_AO_IFACE]	    = &gxbb_ao_iface.hw,

		[CLKID_AO_I2C]		    = &gxbb_ao_i2c.hw,

		[CLKID_SD_EMMC_A]	    = &gxbb_emmc_a.hw,

		[CLKID_SD_EMMC_B]	    = &gxbb_emmc_b.hw,

		[CLKID_SD_EMMC_C]	    = &gxbb_emmc_c.hw,

	},

	.num = NR_CLKS,

};
@@ -847,6 +853,9 @@ static struct clk_gate *gxbb_clk_gates[] = { 
	&gxbb_ao_ahb_bus,

	&gxbb_ao_iface,

	&gxbb_ao_i2c,

	&gxbb_emmc_a,

	&gxbb_emmc_b,

	&gxbb_emmc_c,

};



static int gxbb_clkc_probe(struct platform_device *pdev)

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