KVM: nVMX: postpone VMCS changes on MSR_IA32_APICBASE write (dccbfcf5) · Commits · 戴 / test

If vmcs12 does not intercept APIC_BASE writes, then KVM will handle the write with vmcs02 as the current VMCS. This will incorrectly apply modifications intended for vmcs01 to vmcs02 and L2 can use it to gain access to L0's x2APIC registers by disabling virtualized x2APIC while using msr bitmap that assumes enabled. Postpone execution of vmx_set_virtual_x2apic_mode until vmcs01 is the current VMCS. An alternative solution would temporarily make vmcs01 the current VMCS, but it requires more care. Fixes: ("x86, apicv: add virtual x2apic support") Reported-by:

Jim Mattson <jmattson@google.com> Reviewed-by:

Wanpeng Li <wanpeng.li@hotmail.com> Signed-off-by:

Radim Krčmář <rkrcmar@redhat.com>

arch/x86/kvm/vmx.c

+13 −0

Original line number	Diff line number	Diff line
		@@ -422,6 +422,7 @@ struct nested_vmx {
		struct list_head vmcs02_pool;
		int vmcs02_num;
		u64 vmcs01_tsc_offset;
		bool change_vmcs01_virtual_x2apic_mode;
		/* L2 must run next, and mustn't decide to exit to L1. */
		bool nested_run_pending;
		/*
		@@ -8424,6 +8425,12 @@ static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
		{
		u32 sec_exec_control;

		/* Postpone execution until vmcs01 is the current VMCS. */
		if (is_guest_mode(vcpu)) {
		to_vmx(vcpu)->nested.change_vmcs01_virtual_x2apic_mode = true;
		return;
		}

		/*
		* There is not point to enable virtualize x2apic without enable
		* apicv
		@@ -10749,6 +10756,12 @@ static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
		vmcs_set_bits(PIN_BASED_VM_EXEC_CONTROL,
		PIN_BASED_VMX_PREEMPTION_TIMER);

		if (vmx->nested.change_vmcs01_virtual_x2apic_mode) {
		vmx->nested.change_vmcs01_virtual_x2apic_mode = false;
		vmx_set_virtual_x2apic_mode(vcpu,
		vcpu->arch.apic_base & X2APIC_ENABLE);
		}

		/* This is needed for same reason as it was needed in prepare_vmcs02 */
		vmx->host_rsp = 0;

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