Commit dcc1dd23 authored by Jack Steiner's avatar Jack Steiner Committed by Tony Luck
Browse files

[IA64-SGI] - Eliminate SN pio_phys_xxx macros. Move to assembly 



Rewrite the SN pio_phys_xxx macros in assembly language. This
avoids issues with the Intel icc compiler. Function call
overhead is not an issue - the functions reference PIOs
and take 100's nsec to complete.

In addition, the functions should likely be in assembly
language anyway - they reference memory using physical
addressing mode. One function executes with psr.ic disabled.

Signed-off-by: default avatarJack Steiner <steiner@sgi.com>
Signed-off-by: default avatarTony Luck <tony.luck@intel.com>
parent 412e6a37

arch/ia64/sn/kernel/Makefile

+2 −1
Original line number Diff line number Diff line
@@ -10,7 +10,8 @@ 
CPPFLAGS += -I$(srctree)/arch/ia64/sn/include



obj-y				+= setup.o bte.o bte_error.o irq.o mca.o idle.o \

				   huberror.o io_init.o iomv.o klconflib.o sn2/

				   huberror.o io_init.o iomv.o klconflib.o pio_phys.o \

				   sn2/

obj-$(CONFIG_IA64_GENERIC)      += machvec.o

obj-$(CONFIG_SGI_TIOCX)		+= tiocx.o

obj-$(CONFIG_IA64_SGI_SN_XP)	+= xp.o

arch/ia64/sn/kernel/pio_phys.S

0 → 100644
+71 −0
Original line number Diff line number Diff line 
/*

 * This file is subject to the terms and conditions of the GNU General Public

 * License.  See the file "COPYING" in the main directory of this archive

 * for more details.

 *

 * Copyright (C) 2000-2005 Silicon Graphics, Inc. All rights reserved.

 *

 * This file contains macros used to access MMR registers via

 * uncached physical addresses.

 *      pio_phys_read_mmr  - read an MMR

 *      pio_phys_write_mmr - write an MMR

 *      pio_atomic_phys_write_mmrs - atomically write 1 or 2 MMRs with psr.ic=0

 *              Second MMR will be skipped if address is NULL

 *

 * Addresses passed to these routines should be uncached physical addresses

 * 	ie., 0x80000....

 */







#include <asm/asmmacro.h>

#include <asm/page.h>



GLOBAL_ENTRY(pio_phys_read_mmr)

	.prologue

	.regstk 1,0,0,0

	.body

	mov r2=psr

	rsm psr.i | psr.dt

	;;

	srlz.d

	ld8.acq r8=[r32]

	;;

	mov psr.l=r2;;

	srlz.d

	br.ret.sptk.many rp

END(pio_phys_read_mmr)



GLOBAL_ENTRY(pio_phys_write_mmr)

	.prologue

	.regstk 2,0,0,0

	.body

	mov r2=psr

	rsm psr.i | psr.dt

	;;

	srlz.d

	st8.rel [r32]=r33

	;;

	mov psr.l=r2;;

	srlz.d

	br.ret.sptk.many rp

END(pio_phys_write_mmr)



GLOBAL_ENTRY(pio_atomic_phys_write_mmrs)

	.prologue

	.regstk 4,0,0,0

	.body

	mov r2=psr

	cmp.ne p9,p0=r34,r0;

	rsm psr.i | psr.dt | psr.ic

	;;

	srlz.d

	st8.rel [r32]=r33

(p9)	st8.rel [r34]=r35

	;;

	mov psr.l=r2;;

	srlz.d

	br.ret.sptk.many rp

END(pio_atomic_phys_write_mmrs)

include/asm-ia64/sn/rw_mmr.h

+5 −51
Original line number Diff line number Diff line
@@ -3,15 +3,14 @@ 
 * License.  See the file "COPYING" in the main directory of this archive

 * for more details.

 *

 * Copyright (C) 2002-2004 Silicon Graphics, Inc.  All Rights Reserved.

 * Copyright (C) 2002-2006 Silicon Graphics, Inc.  All Rights Reserved.

 */

#ifndef _ASM_IA64_SN_RW_MMR_H

#define _ASM_IA64_SN_RW_MMR_H





/*

 * This file contains macros used to access MMR registers via

 * uncached physical addresses.

 * This file that access MMRs via uncached physical addresses.

 * 	pio_phys_read_mmr  - read an MMR

 * 	pio_phys_write_mmr - write an MMR

 * 	pio_atomic_phys_write_mmrs - atomically write 1 or 2 MMRs with psr.ic=0
@@ -22,53 +21,8 @@ 
 */





extern inline long

pio_phys_read_mmr(volatile long *mmr) 

{

	long val;

        asm volatile

            ("mov r2=psr;;"

             "rsm psr.i | psr.dt;;"

             "srlz.i;;"

             "ld8.acq %0=[%1];;"

             "mov psr.l=r2;;"

             "srlz.i;;"

             : "=r"(val)

             : "r"(mmr)

	     : "r2");

        return val;

}







extern inline void

pio_phys_write_mmr(volatile long *mmr, long val) 

{

        asm volatile

            ("mov r2=psr;;"

             "rsm psr.i | psr.dt;;"

             "srlz.i;;"

             "st8.rel [%0]=%1;;"

             "mov psr.l=r2;;"

             "srlz.i;;"

	     :: "r"(mmr), "r"(val)

             : "r2", "memory");

}            



extern inline void

pio_atomic_phys_write_mmrs(volatile long *mmr1, long val1, volatile long *mmr2, long val2) 

{

        asm volatile

            ("mov r2=psr;;"

             "rsm psr.i | psr.dt | psr.ic;;"

	     "cmp.ne p9,p0=%2,r0;"

             "srlz.i;;"

             "st8.rel [%0]=%1;"

             "(p9) st8.rel [%2]=%3;;"

             "mov psr.l=r2;;"

             "srlz.i;;"

	     :: "r"(mmr1), "r"(val1), "r"(mmr2), "r"(val2)

             : "p9", "r2", "memory");

}            

extern long pio_phys_read_mmr(volatile long *mmr); 

extern void pio_phys_write_mmr(volatile long *mmr, long val);

extern void pio_atomic_phys_write_mmrs(volatile long *mmr1, long val1, volatile long *mmr2, long val2); 



#endif /* _ASM_IA64_SN_RW_MMR_H */

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