Commit dca463da authored by Lorenzo Pieralisi's avatar Lorenzo Pieralisi
Browse files

ARM: kernel: enhance MPIDR macro definitions 



Kernel subsystems other than the topology layer need the MPIDR
mask definitions to access the MPIDR without relying on hardcoded
masks. This patch moves the MPIDR register masks definition to
a header file and defines a macro to simplify access to MPIDR bit fields
representing affinity levels.

Signed-off-by: default avatarLorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Acked-by: default avatarWill Deacon <will.deacon@arm.com>
Acked-by: default avatarNicolas Pitre <nico@linaro.org>
parent 77b67063

arch/arm/include/asm/cputype.h

+13 −0
Original line number Diff line number Diff line
@@ -25,6 +25,19 @@ 
#define CPUID_EXT_ISAR4	"c2, 4"

#define CPUID_EXT_ISAR5	"c2, 5"



#define MPIDR_SMP_BITMASK (0x3 << 30)

#define MPIDR_SMP_VALUE (0x2 << 30)



#define MPIDR_MT_BITMASK (0x1 << 24)



#define MPIDR_HWID_BITMASK 0xFFFFFF



#define MPIDR_LEVEL_BITS 8

#define MPIDR_LEVEL_MASK ((1 << MPIDR_LEVEL_BITS) - 1)



#define MPIDR_AFFINITY_LEVEL(mpidr, level) \

	((mpidr >> (MPIDR_LEVEL_BITS * level)) & MPIDR_LEVEL_MASK)



extern unsigned int processor_id;



#ifdef CONFIG_CPU_CP15

arch/arm/kernel/topology.c

+1 −26
Original line number Diff line number Diff line
@@ -196,31 +196,6 @@ static inline void parse_dt_topology(void) {} 
static inline void update_cpu_power(unsigned int cpuid, unsigned int mpidr) {}

#endif





/*

 * cpu topology management

 */



#define MPIDR_SMP_BITMASK (0x3 << 30)

#define MPIDR_SMP_VALUE (0x2 << 30)



#define MPIDR_MT_BITMASK (0x1 << 24)



/*

 * These masks reflect the current use of the affinity levels.

 * The affinity level can be up to 16 bits according to ARM ARM

 */

#define MPIDR_HWID_BITMASK 0xFFFFFF



#define MPIDR_LEVEL0_MASK 0x3

#define MPIDR_LEVEL0_SHIFT 0



#define MPIDR_LEVEL1_MASK 0xF

#define MPIDR_LEVEL1_SHIFT 8



#define MPIDR_LEVEL2_MASK 0xFF

#define MPIDR_LEVEL2_SHIFT 16



 /*

 * cpu topology table

 */

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