Commit dc97997a authored by Chris Wilson's avatar Chris Wilson
Browse files

drm/i915: Use drm_i915_private as the native pointer for intel_uncore.c 



Pass drm_i915_private to the uncore init/fini routines and their
subservients as it is their native type.

   text    data     bss     dec     hex filename
6309978 3578778  696320 10585076         a183f4 vmlinux
6309530 3578778  696320 10584628         a18234 vmlinux

a modest 400 bytes of saving, but 60 lines of code deleted!

Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: default avatarJoonas Lahtinen <joonas.lahtinen@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1462885804-26750-1-git-send-email-chris@chris-wilson.co.uk
parent ac840ae5

drivers/gpu/drm/i915/i915_debugfs.c

+2 −2
Original line number Diff line number Diff line
@@ -4981,7 +4981,7 @@ i915_max_freq_set(void *data, u64 val) 


	dev_priv->rps.max_freq_softlimit = val;



	intel_set_rps(dev, val);

	intel_set_rps(dev_priv, val);



	mutex_unlock(&dev_priv->rps.hw_lock);
@@ -5048,7 +5048,7 @@ i915_min_freq_set(void *data, u64 val) 


	dev_priv->rps.min_freq_softlimit = val;



	intel_set_rps(dev, val);

	intel_set_rps(dev_priv, val);



	mutex_unlock(&dev_priv->rps.hw_lock);

drivers/gpu/drm/i915/i915_dma.c

+7 −6
Original line number Diff line number Diff line
@@ -223,8 +223,7 @@ static int i915_getparam(struct drm_device *dev, void *data, 
			return -ENODEV;

		break;

	case I915_PARAM_HAS_GPU_RESET:

		value = i915.enable_hangcheck &&

			intel_has_gpu_reset(dev);

		value = i915.enable_hangcheck && intel_has_gpu_reset(dev_priv);

		break;

	case I915_PARAM_HAS_RESOURCE_STREAMER:

		value = HAS_RESOURCE_STREAMER(dev);
@@ -427,6 +426,8 @@ static const struct vga_switcheroo_client_ops i915_switcheroo_ops = { 


static void i915_gem_fini(struct drm_device *dev)

{

	struct drm_i915_private *dev_priv = to_i915(dev);



	/*

	 * Neither the BIOS, ourselves or any other kernel

	 * expects the system to be in execlists mode on startup,
@@ -447,7 +448,7 @@ static void i915_gem_fini(struct drm_device *dev) 
	 * machine in an unusable condition.

	 */

	if (HAS_HW_CONTEXTS(dev)) {

		int reset = intel_gpu_reset(dev, ALL_ENGINES);

		int reset = intel_gpu_reset(dev_priv, ALL_ENGINES);

		WARN_ON(reset && reset != -ENODEV);

	}
@@ -1189,7 +1190,7 @@ static int i915_driver_init_mmio(struct drm_i915_private *dev_priv) 
	if (ret < 0)

		goto put_bridge;



	intel_uncore_init(dev);

	intel_uncore_init(dev_priv);



	return 0;
@@ -1207,7 +1208,7 @@ static void i915_driver_cleanup_mmio(struct drm_i915_private *dev_priv) 
{

	struct drm_device *dev = dev_priv->dev;



	intel_uncore_fini(dev);

	intel_uncore_fini(dev_priv);

	i915_mmio_cleanup(dev);

	pci_dev_put(dev_priv->bridge_dev);

}
@@ -1288,7 +1289,7 @@ static int i915_driver_init_hw(struct drm_i915_private *dev_priv) 
	pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY,

			   PM_QOS_DEFAULT_VALUE);



	intel_uncore_sanitize(dev);

	intel_uncore_sanitize(dev_priv);



	intel_opregion_setup(dev);

drivers/gpu/drm/i915/i915_drv.c

+13 −13
Original line number Diff line number Diff line
@@ -606,7 +606,7 @@ static int i915_drm_suspend(struct drm_device *dev) 


	intel_guc_suspend(dev);



	intel_suspend_gt_powersave(dev);

	intel_suspend_gt_powersave(dev_priv);



	intel_display_suspend(dev);
@@ -626,7 +626,7 @@ static int i915_drm_suspend(struct drm_device *dev) 
	opregion_target_state = suspend_to_idle(dev_priv) ? PCI_D1 : PCI_D3cold;

	intel_opregion_notify_adapter(dev, opregion_target_state);



	intel_uncore_forcewake_reset(dev, false);

	intel_uncore_forcewake_reset(dev_priv, false);

	intel_opregion_fini(dev);



	intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED, true);
@@ -866,9 +866,9 @@ static int i915_drm_resume_early(struct drm_device *dev) 
		DRM_ERROR("Resume prepare failed: %d, continuing anyway\n",

			  ret);



	intel_uncore_early_sanitize(dev, true);

	intel_uncore_early_sanitize(dev_priv, true);



	if (IS_BROXTON(dev)) {

	if (IS_BROXTON(dev_priv)) {

		if (!dev_priv->suspended_to_idle)

			gen9_sanitize_dc_state(dev_priv);

		bxt_disable_dc9(dev_priv);
@@ -876,7 +876,7 @@ static int i915_drm_resume_early(struct drm_device *dev) 
		hsw_disable_pc8(dev_priv);

	}



	intel_uncore_sanitize(dev);

	intel_uncore_sanitize(dev_priv);



	if (IS_BROXTON(dev_priv) ||

	    !(dev_priv->suspended_to_idle && dev_priv->csr.dmc_payload))
@@ -926,7 +926,7 @@ int i915_reset(struct drm_i915_private *dev_priv) 
	unsigned reset_counter;

	int ret;



	intel_reset_gt_powersave(dev);

	intel_reset_gt_powersave(dev_priv);



	mutex_lock(&dev->struct_mutex);
@@ -942,7 +942,7 @@ int i915_reset(struct drm_i915_private *dev_priv) 


	i915_gem_reset(dev);



	ret = intel_gpu_reset(dev, ALL_ENGINES);

	ret = intel_gpu_reset(dev_priv, ALL_ENGINES);



	/* Also reset the gpu hangman. */

	if (error->stop_rings != 0) {
@@ -997,7 +997,7 @@ int i915_reset(struct drm_i915_private *dev_priv) 
	 * of re-init after reset.

	 */

	if (INTEL_INFO(dev)->gen > 5)

		intel_enable_gt_powersave(dev);

		intel_enable_gt_powersave(dev_priv);



	return 0;
@@ -1474,7 +1474,7 @@ static int intel_runtime_suspend(struct device *device) 
	struct drm_i915_private *dev_priv = dev->dev_private;

	int ret;



	if (WARN_ON_ONCE(!(dev_priv->rps.enabled && intel_enable_rc6(dev))))

	if (WARN_ON_ONCE(!(dev_priv->rps.enabled && intel_enable_rc6())))

		return -ENODEV;



	if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev)))
@@ -1513,7 +1513,7 @@ static int intel_runtime_suspend(struct device *device) 


	intel_guc_suspend(dev);



	intel_suspend_gt_powersave(dev);

	intel_suspend_gt_powersave(dev_priv);

	intel_runtime_pm_disable_interrupts(dev_priv);



	ret = 0;
@@ -1535,7 +1535,7 @@ static int intel_runtime_suspend(struct device *device) 
		return ret;

	}



	intel_uncore_forcewake_reset(dev, false);

	intel_uncore_forcewake_reset(dev_priv, false);



	enable_rpm_wakeref_asserts(dev_priv);

	WARN_ON_ONCE(atomic_read(&dev_priv->pm.wakeref_count));
@@ -1616,7 +1616,7 @@ static int intel_runtime_resume(struct device *device) 
	 * we can do is to hope that things will still work (and disable RPM).

	 */

	i915_gem_init_swizzling(dev);

	gen6_update_ring_freq(dev);

	gen6_update_ring_freq(dev_priv);



	intel_runtime_pm_enable_interrupts(dev_priv);
@@ -1628,7 +1628,7 @@ static int intel_runtime_resume(struct device *device) 
	if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))

		intel_hpd_init(dev_priv);



	intel_enable_gt_powersave(dev);

	intel_enable_gt_powersave(dev_priv);



	enable_rpm_wakeref_asserts(dev_priv);

drivers/gpu/drm/i915/i915_drv.h

+9 −9
Original line number Diff line number Diff line
@@ -2777,8 +2777,8 @@ extern void i915_driver_postclose(struct drm_device *dev, 
extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,

			      unsigned long arg);

#endif

extern int intel_gpu_reset(struct drm_device *dev, u32 engine_mask);

extern bool intel_has_gpu_reset(struct drm_device *dev);

extern int intel_gpu_reset(struct drm_i915_private *dev_priv, u32 engine_mask);

extern bool intel_has_gpu_reset(struct drm_i915_private *dev_priv);

extern int i915_reset(struct drm_i915_private *dev_priv);

extern int intel_guc_reset(struct drm_i915_private *dev_priv);

extern void intel_engine_init_hangcheck(struct intel_engine_cs *engine);
@@ -2807,14 +2807,15 @@ extern void intel_irq_init(struct drm_i915_private *dev_priv); 
int intel_irq_install(struct drm_i915_private *dev_priv);

void intel_irq_uninstall(struct drm_i915_private *dev_priv);



extern void intel_uncore_sanitize(struct drm_device *dev);

extern void intel_uncore_early_sanitize(struct drm_device *dev,

extern void intel_uncore_sanitize(struct drm_i915_private *dev_priv);

extern void intel_uncore_early_sanitize(struct drm_i915_private *dev_priv,

					bool restore_forcewake);

extern void intel_uncore_init(struct drm_device *dev);

extern void intel_uncore_init(struct drm_i915_private *dev_priv);

extern bool intel_uncore_unclaimed_mmio(struct drm_i915_private *dev_priv);

extern bool intel_uncore_arm_unclaimed_mmio_detection(struct drm_i915_private *dev_priv);

extern void intel_uncore_fini(struct drm_device *dev);

extern void intel_uncore_forcewake_reset(struct drm_device *dev, bool restore);

extern void intel_uncore_fini(struct drm_i915_private *dev_priv);

extern void intel_uncore_forcewake_reset(struct drm_i915_private *dev_priv,

					 bool restore);

const char *intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id);

void intel_uncore_forcewake_get(struct drm_i915_private *dev_priv,

				enum forcewake_domains domains);
@@ -3547,11 +3548,10 @@ extern void i915_redisable_vga(struct drm_device *dev); 
extern void i915_redisable_vga_power_on(struct drm_device *dev);

extern bool ironlake_set_drps(struct drm_i915_private *dev_priv, u8 val);

extern void intel_init_pch_refclk(struct drm_device *dev);

extern void intel_set_rps(struct drm_device *dev, u8 val);

extern void intel_set_rps(struct drm_i915_private *dev_priv, u8 val);

extern void intel_set_memory_cxsr(struct drm_i915_private *dev_priv,

				  bool enable);

extern void intel_detect_pch(struct drm_device *dev);

extern int intel_enable_rc6(const struct drm_device *dev);



extern bool i915_semaphore_is_enabled(struct drm_i915_private *dev_priv);

int i915_reg_read_ioctl(struct drm_device *dev, void *data,

drivers/gpu/drm/i915/i915_gem_gtt.c

+4 −5
Original line number Diff line number Diff line
@@ -2279,12 +2279,11 @@ static void undo_idling(struct drm_i915_private *dev_priv, bool interruptible) 
		dev_priv->mm.interruptible = interruptible;

}



void i915_check_and_clear_faults(struct drm_device *dev)

void i915_check_and_clear_faults(struct drm_i915_private *dev_priv)

{

	struct drm_i915_private *dev_priv = dev->dev_private;

	struct intel_engine_cs *engine;



	if (INTEL_INFO(dev)->gen < 6)

	if (INTEL_INFO(dev_priv)->gen < 6)

		return;



	for_each_engine(engine, dev_priv) {
@@ -2328,7 +2327,7 @@ void i915_gem_suspend_gtt_mappings(struct drm_device *dev) 
	if (INTEL_INFO(dev)->gen < 6)

		return;



	i915_check_and_clear_faults(dev);

	i915_check_and_clear_faults(dev_priv);



	ggtt->base.clear_range(&ggtt->base, ggtt->base.start, ggtt->base.total,

			     true);
@@ -3248,7 +3247,7 @@ void i915_gem_restore_gtt_mappings(struct drm_device *dev) 
	struct i915_vma *vma;

	bool flush;



	i915_check_and_clear_faults(dev);

	i915_check_and_clear_faults(dev_priv);



	/* First fill our portion of the GTT with scratch pages */

	ggtt->base.clear_range(&ggtt->base, ggtt->base.start, ggtt->base.total,

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