Commit dc745ece authored by Russell King's avatar Russell King Committed by David S. Miller
Browse files

net: dsa: mv88e6xxx: remove port_link_state functions 



The port_link_state method is only used by mv88e6xxx_port_setup_mac(),
which is now only called during port setup, rather than also being
called via phylink's mac_config method.

Remove this now unnecessary optimisation, which allows us to remove the
port_link_state methods as well.

Signed-off-by: default avatarRussell King <rmk+kernel@armlinux.org.uk>
Reviewed-by: default avatarAndrew Lunn <andrew@lunn.ch>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent f365c6f7

drivers/net/dsa/mv88e6xxx/chip.c

+0 −46
Original line number Diff line number Diff line
@@ -423,30 +423,11 @@ static int mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip *chip, int port, 
				    int link, int speed, int duplex, int pause,

				    phy_interface_t mode)

{

	struct phylink_link_state state;

	int err;



	if (!chip->info->ops->port_set_link)

		return 0;



	if (!chip->info->ops->port_link_state)

		return 0;



	err = chip->info->ops->port_link_state(chip, port, &state);

	if (err)

		return err;



	/* Has anything actually changed? We don't expect the

	 * interface mode to change without one of the other

	 * parameters also changing

	 */

	if (state.link == link &&

	    state.speed == speed &&

	    state.duplex == duplex &&

	    (state.interface == mode ||

	     state.interface == PHY_INTERFACE_MODE_NA))

		return 0;



	/* Port's MAC control must not be changed unless the link is down */

	err = chip->info->ops->port_set_link(chip, port, LINK_FORCED_DOWN);

	if (err)
@@ -3411,7 +3392,6 @@ static const struct mv88e6xxx_ops mv88e6085_ops = { 
	.port_pause_limit = mv88e6097_port_pause_limit,

	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,

	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,

	.port_link_state = mv88e6352_port_link_state,

	.port_get_cmode = mv88e6185_port_get_cmode,

	.port_setup_message_port = mv88e6xxx_setup_message_port,

	.stats_snapshot = mv88e6xxx_g1_stats_snapshot,
@@ -3445,7 +3425,6 @@ static const struct mv88e6xxx_ops mv88e6095_ops = { 
	.port_set_frame_mode = mv88e6085_port_set_frame_mode,

	.port_set_egress_floods = mv88e6185_port_set_egress_floods,

	.port_set_upstream_port = mv88e6095_port_set_upstream_port,

	.port_link_state = mv88e6185_port_link_state,

	.port_get_cmode = mv88e6185_port_get_cmode,

	.port_setup_message_port = mv88e6xxx_setup_message_port,

	.stats_snapshot = mv88e6xxx_g1_stats_snapshot,
@@ -3481,7 +3460,6 @@ static const struct mv88e6xxx_ops mv88e6097_ops = { 
	.port_pause_limit = mv88e6097_port_pause_limit,

	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,

	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,

	.port_link_state = mv88e6352_port_link_state,

	.port_get_cmode = mv88e6185_port_get_cmode,

	.port_setup_message_port = mv88e6xxx_setup_message_port,

	.stats_snapshot = mv88e6xxx_g1_stats_snapshot,
@@ -3515,7 +3493,6 @@ static const struct mv88e6xxx_ops mv88e6123_ops = { 
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,

	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,

	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,

	.port_link_state = mv88e6352_port_link_state,

	.port_get_cmode = mv88e6185_port_get_cmode,

	.port_setup_message_port = mv88e6xxx_setup_message_port,

	.stats_snapshot = mv88e6320_g1_stats_snapshot,
@@ -3554,7 +3531,6 @@ static const struct mv88e6xxx_ops mv88e6131_ops = { 
	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,

	.port_pause_limit = mv88e6097_port_pause_limit,

	.port_set_pause = mv88e6185_port_set_pause,

	.port_link_state = mv88e6352_port_link_state,

	.port_get_cmode = mv88e6185_port_get_cmode,

	.port_setup_message_port = mv88e6xxx_setup_message_port,

	.stats_snapshot = mv88e6xxx_g1_stats_snapshot,
@@ -3598,7 +3574,6 @@ static const struct mv88e6xxx_ops mv88e6141_ops = { 
	.port_pause_limit = mv88e6097_port_pause_limit,

	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,

	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,

	.port_link_state = mv88e6352_port_link_state,

	.port_get_cmode = mv88e6352_port_get_cmode,

	.port_set_cmode = mv88e6341_port_set_cmode,

	.port_setup_message_port = mv88e6xxx_setup_message_port,
@@ -3648,7 +3623,6 @@ static const struct mv88e6xxx_ops mv88e6161_ops = { 
	.port_pause_limit = mv88e6097_port_pause_limit,

	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,

	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,

	.port_link_state = mv88e6352_port_link_state,

	.port_get_cmode = mv88e6185_port_get_cmode,

	.port_setup_message_port = mv88e6xxx_setup_message_port,

	.stats_snapshot = mv88e6xxx_g1_stats_snapshot,
@@ -3683,7 +3657,6 @@ static const struct mv88e6xxx_ops mv88e6165_ops = { 
	.port_set_speed_duplex = mv88e6185_port_set_speed_duplex,

	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,

	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,

	.port_link_state = mv88e6352_port_link_state,

	.port_get_cmode = mv88e6185_port_get_cmode,

	.port_setup_message_port = mv88e6xxx_setup_message_port,

	.stats_snapshot = mv88e6xxx_g1_stats_snapshot,
@@ -3726,7 +3699,6 @@ static const struct mv88e6xxx_ops mv88e6171_ops = { 
	.port_pause_limit = mv88e6097_port_pause_limit,

	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,

	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,

	.port_link_state = mv88e6352_port_link_state,

	.port_get_cmode = mv88e6352_port_get_cmode,

	.port_setup_message_port = mv88e6xxx_setup_message_port,

	.stats_snapshot = mv88e6320_g1_stats_snapshot,
@@ -3770,7 +3742,6 @@ static const struct mv88e6xxx_ops mv88e6172_ops = { 
	.port_pause_limit = mv88e6097_port_pause_limit,

	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,

	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,

	.port_link_state = mv88e6352_port_link_state,

	.port_get_cmode = mv88e6352_port_get_cmode,

	.port_setup_message_port = mv88e6xxx_setup_message_port,

	.stats_snapshot = mv88e6320_g1_stats_snapshot,
@@ -3821,7 +3792,6 @@ static const struct mv88e6xxx_ops mv88e6175_ops = { 
	.port_pause_limit = mv88e6097_port_pause_limit,

	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,

	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,

	.port_link_state = mv88e6352_port_link_state,

	.port_get_cmode = mv88e6352_port_get_cmode,

	.port_setup_message_port = mv88e6xxx_setup_message_port,

	.stats_snapshot = mv88e6320_g1_stats_snapshot,
@@ -3865,7 +3835,6 @@ static const struct mv88e6xxx_ops mv88e6176_ops = { 
	.port_pause_limit = mv88e6097_port_pause_limit,

	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,

	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,

	.port_link_state = mv88e6352_port_link_state,

	.port_get_cmode = mv88e6352_port_get_cmode,

	.port_setup_message_port = mv88e6xxx_setup_message_port,

	.stats_snapshot = mv88e6320_g1_stats_snapshot,
@@ -3913,7 +3882,6 @@ static const struct mv88e6xxx_ops mv88e6185_ops = { 
	.port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting,

	.port_set_upstream_port = mv88e6095_port_set_upstream_port,

	.port_set_pause = mv88e6185_port_set_pause,

	.port_link_state = mv88e6185_port_link_state,

	.port_get_cmode = mv88e6185_port_get_cmode,

	.port_setup_message_port = mv88e6xxx_setup_message_port,

	.stats_snapshot = mv88e6xxx_g1_stats_snapshot,
@@ -3955,7 +3923,6 @@ static const struct mv88e6xxx_ops mv88e6190_ops = { 
	.port_pause_limit = mv88e6390_port_pause_limit,

	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,

	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,

	.port_link_state = mv88e6352_port_link_state,

	.port_get_cmode = mv88e6352_port_get_cmode,

	.port_set_cmode = mv88e6390_port_set_cmode,

	.port_setup_message_port = mv88e6xxx_setup_message_port,
@@ -4015,7 +3982,6 @@ static const struct mv88e6xxx_ops mv88e6190x_ops = { 
	.port_pause_limit = mv88e6390_port_pause_limit,

	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,

	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,

	.port_link_state = mv88e6352_port_link_state,

	.port_get_cmode = mv88e6352_port_get_cmode,

	.port_set_cmode = mv88e6390x_port_set_cmode,

	.port_setup_message_port = mv88e6xxx_setup_message_port,
@@ -4074,7 +4040,6 @@ static const struct mv88e6xxx_ops mv88e6191_ops = { 
	.port_pause_limit = mv88e6390_port_pause_limit,

	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,

	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,

	.port_link_state = mv88e6352_port_link_state,

	.port_get_cmode = mv88e6352_port_get_cmode,

	.port_set_cmode = mv88e6390_port_set_cmode,

	.port_setup_message_port = mv88e6xxx_setup_message_port,
@@ -4137,7 +4102,6 @@ static const struct mv88e6xxx_ops mv88e6240_ops = { 
	.port_pause_limit = mv88e6097_port_pause_limit,

	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,

	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,

	.port_link_state = mv88e6352_port_link_state,

	.port_get_cmode = mv88e6352_port_get_cmode,

	.port_setup_message_port = mv88e6xxx_setup_message_port,

	.stats_snapshot = mv88e6320_g1_stats_snapshot,
@@ -4193,7 +4157,6 @@ static const struct mv88e6xxx_ops mv88e6250_ops = { 
	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,

	.port_pause_limit = mv88e6097_port_pause_limit,

	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,

	.port_link_state = mv88e6250_port_link_state,

	.stats_snapshot = mv88e6320_g1_stats_snapshot,

	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,

	.stats_get_sset_count = mv88e6250_stats_get_sset_count,
@@ -4233,7 +4196,6 @@ static const struct mv88e6xxx_ops mv88e6290_ops = { 
	.port_pause_limit = mv88e6390_port_pause_limit,

	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,

	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,

	.port_link_state = mv88e6352_port_link_state,

	.port_get_cmode = mv88e6352_port_get_cmode,

	.port_set_cmode = mv88e6390_port_set_cmode,

	.port_setup_message_port = mv88e6xxx_setup_message_port,
@@ -4295,7 +4257,6 @@ static const struct mv88e6xxx_ops mv88e6320_ops = { 
	.port_pause_limit = mv88e6097_port_pause_limit,

	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,

	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,

	.port_link_state = mv88e6352_port_link_state,

	.port_get_cmode = mv88e6352_port_get_cmode,

	.port_setup_message_port = mv88e6xxx_setup_message_port,

	.stats_snapshot = mv88e6320_g1_stats_snapshot,
@@ -4338,7 +4299,6 @@ static const struct mv88e6xxx_ops mv88e6321_ops = { 
	.port_pause_limit = mv88e6097_port_pause_limit,

	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,

	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,

	.port_link_state = mv88e6352_port_link_state,

	.port_get_cmode = mv88e6352_port_get_cmode,

	.port_setup_message_port = mv88e6xxx_setup_message_port,

	.stats_snapshot = mv88e6320_g1_stats_snapshot,
@@ -4381,7 +4341,6 @@ static const struct mv88e6xxx_ops mv88e6341_ops = { 
	.port_pause_limit = mv88e6097_port_pause_limit,

	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,

	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,

	.port_link_state = mv88e6352_port_link_state,

	.port_get_cmode = mv88e6352_port_get_cmode,

	.port_set_cmode = mv88e6341_port_set_cmode,

	.port_setup_message_port = mv88e6xxx_setup_message_port,
@@ -4434,7 +4393,6 @@ static const struct mv88e6xxx_ops mv88e6350_ops = { 
	.port_pause_limit = mv88e6097_port_pause_limit,

	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,

	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,

	.port_link_state = mv88e6352_port_link_state,

	.port_get_cmode = mv88e6352_port_get_cmode,

	.port_setup_message_port = mv88e6xxx_setup_message_port,

	.stats_snapshot = mv88e6320_g1_stats_snapshot,
@@ -4475,7 +4433,6 @@ static const struct mv88e6xxx_ops mv88e6351_ops = { 
	.port_pause_limit = mv88e6097_port_pause_limit,

	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,

	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,

	.port_link_state = mv88e6352_port_link_state,

	.port_get_cmode = mv88e6352_port_get_cmode,

	.port_setup_message_port = mv88e6xxx_setup_message_port,

	.stats_snapshot = mv88e6320_g1_stats_snapshot,
@@ -4521,7 +4478,6 @@ static const struct mv88e6xxx_ops mv88e6352_ops = { 
	.port_pause_limit = mv88e6097_port_pause_limit,

	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,

	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,

	.port_link_state = mv88e6352_port_link_state,

	.port_get_cmode = mv88e6352_port_get_cmode,

	.port_setup_message_port = mv88e6xxx_setup_message_port,

	.stats_snapshot = mv88e6320_g1_stats_snapshot,
@@ -4583,7 +4539,6 @@ static const struct mv88e6xxx_ops mv88e6390_ops = { 
	.port_pause_limit = mv88e6390_port_pause_limit,

	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,

	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,

	.port_link_state = mv88e6352_port_link_state,

	.port_get_cmode = mv88e6352_port_get_cmode,

	.port_set_cmode = mv88e6390_port_set_cmode,

	.port_setup_message_port = mv88e6xxx_setup_message_port,
@@ -4647,7 +4602,6 @@ static const struct mv88e6xxx_ops mv88e6390x_ops = { 
	.port_pause_limit = mv88e6390_port_pause_limit,

	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,

	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,

	.port_link_state = mv88e6352_port_link_state,

	.port_get_cmode = mv88e6352_port_get_cmode,

	.port_set_cmode = mv88e6390x_port_set_cmode,

	.port_setup_message_port = mv88e6xxx_setup_message_port,

drivers/net/dsa/mv88e6xxx/chip.h

+0 −3
Original line number Diff line number Diff line
@@ -458,9 +458,6 @@ struct mv88e6xxx_ops { 
	 */

	int (*port_set_upstream_port)(struct mv88e6xxx_chip *chip, int port,

				      int upstream_port);

	/* Return the port link state, as required by phylink */

	int (*port_link_state)(struct mv88e6xxx_chip *chip, int port,

			       struct phylink_link_state *state);



	/* Snapshot the statistics for a port. The statistics can then

	 * be read back a leisure but still with a consistent view.

drivers/net/dsa/mv88e6xxx/port.c

+0 −177
Original line number Diff line number Diff line
@@ -584,183 +584,6 @@ int mv88e6352_port_get_cmode(struct mv88e6xxx_chip *chip, int port, u8 *cmode) 
	return 0;

}



int mv88e6250_port_link_state(struct mv88e6xxx_chip *chip, int port,

			      struct phylink_link_state *state)

{

	int err;

	u16 reg;



	err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, &reg);

	if (err)

		return err;



	if (port < 5) {

		switch (reg & MV88E6250_PORT_STS_PORTMODE_MASK) {

		case MV88E6250_PORT_STS_PORTMODE_PHY_10_HALF:

			state->speed = SPEED_10;

			state->duplex = DUPLEX_HALF;

			break;

		case MV88E6250_PORT_STS_PORTMODE_PHY_100_HALF:

			state->speed = SPEED_100;

			state->duplex = DUPLEX_HALF;

			break;

		case MV88E6250_PORT_STS_PORTMODE_PHY_10_FULL:

			state->speed = SPEED_10;

			state->duplex = DUPLEX_FULL;

			break;

		case MV88E6250_PORT_STS_PORTMODE_PHY_100_FULL:

			state->speed = SPEED_100;

			state->duplex = DUPLEX_FULL;

			break;

		default:

			state->speed = SPEED_UNKNOWN;

			state->duplex = DUPLEX_UNKNOWN;

			break;

		}

	} else {

		switch (reg & MV88E6250_PORT_STS_PORTMODE_MASK) {

		case MV88E6250_PORT_STS_PORTMODE_MII_10_HALF:

			state->speed = SPEED_10;

			state->duplex = DUPLEX_HALF;

			break;

		case MV88E6250_PORT_STS_PORTMODE_MII_100_HALF:

			state->speed = SPEED_100;

			state->duplex = DUPLEX_HALF;

			break;

		case MV88E6250_PORT_STS_PORTMODE_MII_10_FULL:

			state->speed = SPEED_10;

			state->duplex = DUPLEX_FULL;

			break;

		case MV88E6250_PORT_STS_PORTMODE_MII_100_FULL:

			state->speed = SPEED_100;

			state->duplex = DUPLEX_FULL;

			break;

		default:

			state->speed = SPEED_UNKNOWN;

			state->duplex = DUPLEX_UNKNOWN;

			break;

		}

	}



	state->link = !!(reg & MV88E6250_PORT_STS_LINK);

	state->an_enabled = 1;

	state->an_complete = state->link;

	state->interface = PHY_INTERFACE_MODE_NA;



	return 0;

}



int mv88e6352_port_link_state(struct mv88e6xxx_chip *chip, int port,

			      struct phylink_link_state *state)

{

	int err;

	u16 reg;



	switch (chip->ports[port].cmode) {

	case MV88E6XXX_PORT_STS_CMODE_RGMII:

		err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_MAC_CTL,

					  &reg);

		if (err)

			return err;



		if ((reg & MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_RXCLK) &&

		    (reg & MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_TXCLK))

			state->interface = PHY_INTERFACE_MODE_RGMII_ID;

		else if (reg & MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_RXCLK)

			state->interface = PHY_INTERFACE_MODE_RGMII_RXID;

		else if (reg & MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_TXCLK)

			state->interface = PHY_INTERFACE_MODE_RGMII_TXID;

		else

			state->interface = PHY_INTERFACE_MODE_RGMII;

		break;

	case MV88E6XXX_PORT_STS_CMODE_1000BASEX:

		state->interface = PHY_INTERFACE_MODE_1000BASEX;

		break;

	case MV88E6XXX_PORT_STS_CMODE_SGMII:

		state->interface = PHY_INTERFACE_MODE_SGMII;

		break;

	case MV88E6XXX_PORT_STS_CMODE_2500BASEX:

		state->interface = PHY_INTERFACE_MODE_2500BASEX;

		break;

	case MV88E6XXX_PORT_STS_CMODE_XAUI:

		state->interface = PHY_INTERFACE_MODE_XAUI;

		break;

	case MV88E6XXX_PORT_STS_CMODE_RXAUI:

		state->interface = PHY_INTERFACE_MODE_RXAUI;

		break;

	default:

		/* we do not support other cmode values here */

		state->interface = PHY_INTERFACE_MODE_NA;

	}



	err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, &reg);

	if (err)

		return err;



	switch (reg & MV88E6XXX_PORT_STS_SPEED_MASK) {

	case MV88E6XXX_PORT_STS_SPEED_10:

		state->speed = SPEED_10;

		break;

	case MV88E6XXX_PORT_STS_SPEED_100:

		state->speed = SPEED_100;

		break;

	case MV88E6XXX_PORT_STS_SPEED_1000:

		state->speed = SPEED_1000;

		break;

	case MV88E6XXX_PORT_STS_SPEED_10000:

		if ((reg & MV88E6XXX_PORT_STS_CMODE_MASK) ==

		    MV88E6XXX_PORT_STS_CMODE_2500BASEX)

			state->speed = SPEED_2500;

		else

			state->speed = SPEED_10000;

		break;

	}



	state->duplex = reg & MV88E6XXX_PORT_STS_DUPLEX ?

			DUPLEX_FULL : DUPLEX_HALF;

	state->link = !!(reg & MV88E6XXX_PORT_STS_LINK);

	state->an_enabled = 1;

	state->an_complete = state->link;



	return 0;

}



int mv88e6185_port_link_state(struct mv88e6xxx_chip *chip, int port,

			      struct phylink_link_state *state)

{

	if (state->interface == PHY_INTERFACE_MODE_1000BASEX) {

		u8 cmode = chip->ports[port].cmode;



		/* When a port is in "Cross-chip serdes" mode, it uses

		 * 1000Base-X full duplex mode, but there is no automatic

		 * link detection. Use the sync OK status for link (as it

		 * would do for 1000Base-X mode.)

		 */

		if (cmode == MV88E6185_PORT_STS_CMODE_SERDES) {

			u16 mac;

			int err;



			err = mv88e6xxx_port_read(chip, port,

						  MV88E6XXX_PORT_MAC_CTL, &mac);

			if (err)

				return err;



			state->link = !!(mac & MV88E6185_PORT_MAC_CTL_SYNC_OK);

			state->an_enabled = 1;

			state->an_complete =

				!!(mac & MV88E6185_PORT_MAC_CTL_AN_DONE);

			state->duplex =

				state->link ? DUPLEX_FULL : DUPLEX_UNKNOWN;

			state->speed =

				state->link ? SPEED_1000 : SPEED_UNKNOWN;



			return 0;

		}

	}



	return mv88e6352_port_link_state(chip, port, state);

}



/* Offset 0x02: Jamming Control

 *

 * Do not limit the period of time that this port can be paused for by

drivers/net/dsa/mv88e6xxx/port.h

+0 −6
Original line number Diff line number Diff line
@@ -364,12 +364,6 @@ int mv88e6390x_port_set_cmode(struct mv88e6xxx_chip *chip, int port, 
			      phy_interface_t mode);

int mv88e6185_port_get_cmode(struct mv88e6xxx_chip *chip, int port, u8 *cmode);

int mv88e6352_port_get_cmode(struct mv88e6xxx_chip *chip, int port, u8 *cmode);

int mv88e6185_port_link_state(struct mv88e6xxx_chip *chip, int port,

			      struct phylink_link_state *state);

int mv88e6250_port_link_state(struct mv88e6xxx_chip *chip, int port,

			      struct phylink_link_state *state);

int mv88e6352_port_link_state(struct mv88e6xxx_chip *chip, int port,

			      struct phylink_link_state *state);

int mv88e6xxx_port_set_map_da(struct mv88e6xxx_chip *chip, int port);

int mv88e6095_port_set_upstream_port(struct mv88e6xxx_chip *chip, int port,

				     int upstream_port);

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