Commit dc643a84 authored by Geert Uytterhoeven's avatar Geert Uytterhoeven
Browse files

clk: renesas: r8a77990: Correct RCLK handling 



According to R-Car Gen3 Hardware Manual Rev.1.00, R-Car E3 has the
RCLK Frequency Control Register (RCKCR), which determines the OSC and
RINT predivider values, and selection of the RCLK clock source between
RINT and the On-Chip Oscillator.

Hence change the OSC and RINT clock definitions to use the RCKCR
divider, and add the missing On-Chip Oscillator and RCLK clock source
switching logic.

Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: default avatarSimon Horman <horms+renesas@verge.net.au>
parent b9d0b84b

drivers/clk/renesas/r8a77990-cpg-mssr.c

+10 −2
Original line number Diff line number Diff line
@@ -44,6 +44,8 @@ enum clk_ids { 
	CLK_S2,

	CLK_S3,

	CLK_SDSRC,

	CLK_RINT,

	CLK_OCO,



	/* Module Clocks */

	MOD_CLK_BASE
@@ -72,6 +74,10 @@ static const struct cpg_core_clk r8a77990_core_clks[] __initconst = { 
	DEF_FIXED(".s3",       CLK_S3,             CLK_PLL1,       6, 1),

	DEF_FIXED(".sdsrc",    CLK_SDSRC,          CLK_PLL1,       2, 1),



	DEF_DIV6_RO(".r",      CLK_RINT,           CLK_EXTAL, CPG_RCKCR, 32),



	DEF_RATE(".oco",       CLK_OCO,            8 * 1000 * 1000),



	/* Core Clock Outputs */

	DEF_FIXED("za2",       R8A77990_CLK_ZA2,   CLK_PLL0D24,    1, 1),

	DEF_FIXED("za8",       R8A77990_CLK_ZA8,   CLK_PLL0D8,     1, 1),
@@ -100,8 +106,8 @@ static const struct cpg_core_clk r8a77990_core_clks[] __initconst = { 
	DEF_FIXED("cl",        R8A77990_CLK_CL,    CLK_PLL1,      48, 1),

	DEF_FIXED("cp",        R8A77990_CLK_CP,    CLK_EXTAL,      2, 1),

	DEF_FIXED("cpex",      R8A77990_CLK_CPEX,  CLK_EXTAL,      4, 1),

	DEF_FIXED("osc",       R8A77990_CLK_OSC,   CLK_EXTAL,    384, 1),

	DEF_FIXED("r",         R8A77990_CLK_R,     CLK_EXTAL,   1536, 1),



	DEF_DIV6_RO("osc",     R8A77990_CLK_OSC,   CLK_EXTAL, CPG_RCKCR,  8),



	DEF_GEN3_PE("s0d6c",   R8A77990_CLK_S0D6C, CLK_S0, 6, CLK_PE, 2),

	DEF_GEN3_PE("s3d1c",   R8A77990_CLK_S3D1C, CLK_S3, 1, CLK_PE, 1),
@@ -111,6 +117,8 @@ static const struct cpg_core_clk r8a77990_core_clks[] __initconst = { 
	DEF_DIV6P1("canfd",    R8A77990_CLK_CANFD, CLK_PLL0D6, 0x244),

	DEF_DIV6P1("csi0",     R8A77990_CLK_CSI0,  CLK_PLL1D2, 0x00c),

	DEF_DIV6P1("mso",      R8A77990_CLK_MSO,   CLK_PLL1D2, 0x014),



	DEF_GEN3_RCKSEL("r",   R8A77990_CLK_R, CLK_RINT, 1, CLK_OCO, 61 * 4),

};



static const struct mssr_mod_clk r8a77990_mod_clks[] __initconst = {

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