Commit dc4c4bf1 authored Aug 17, 2020 by Rajmohan Mani Committed by Mika Westerberg Sep 03, 2020

thunderbolt: Optimize Force Power logic



Currently the "Force Power" logic uses 10 retries, each with a delay of
250 ms. Thunderbolt controllers in Ice Lake and Tiger Lake platforms are
found to complete this in the order of 3 ms or so. Since this delay
is in resume path, surplus delay is effectively affecting runtime PM
resume flows.

Decrease the granularity of the delay to 3 ms and increase the number of
retries so we wait maximum of ~1 s which is the recommended timeout.
This should make runtime resume a bit faster.

Reported-by: Dana Alkattan <dana.alkattan@intel.com>
Signed-off-by: Rajmohan Mani <rajmohan.mani@intel.com>
Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>

parent fff15f23

drivers/thunderbolt/nhi_ops.c

+2 −2

Original line number	Diff line number	Diff line
		@@ -59,7 +59,7 @@ static int icl_nhi_force_power(struct tb_nhi *nhi, bool power)
		pci_write_config_dword(nhi->pdev, VS_CAP_22, vs_cap);

		if (power) {
		unsigned int retries = 10;
		unsigned int retries = 350;
		u32 val;

		/* Wait until the firmware tells it is up and running */
		@@ -67,7 +67,7 @@ static int icl_nhi_force_power(struct tb_nhi *nhi, bool power)
		pci_read_config_dword(nhi->pdev, VS_CAP_9, &val);
		if (val & VS_CAP_9_FW_READY)
		return 0;
		msleep(250);
		usleep_range(3000, 3100);
		} while (--retries);

		return -ETIMEDOUT;

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