Commit dbeb1a8f authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux 

Pull clk fixes from Stephen Boyd:

 - build fix to export the clk_bulk_prepare() symbol

 - suspend fix for Samsung Exynos SoCs where we need to keep clks on
   across suspend

 - two critical clk markings for clks that shouldn't ever turn off on
   Rockchip SoCs

 - a fix for a copy-paste mistake on Rockchip rk3128 causing some clks
   to touch the same bit and trample over one another

* tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux:
  clk: samsung: exynos4: Enable VPLL and EPLL clocks for suspend/resume cycle
  clk: Export clk_bulk_prepare()
  clk: rockchip: add sclk_timer5 as critical clock on rk3128
  clk: rockchip: fix up rk3128 pvtm and mipi_24m gate regs error
  clk: rockchip: add pclk_pmu as critical clock on rk3128
parents ed0f72f4 5dcbeca6

drivers/clk/clk-bulk.c

+1 −0
Original line number Original line Diff line number Diff line
@@ -105,6 +105,7 @@ err: 




	return  ret;

	return  ret;

}

}

EXPORT_SYMBOL_GPL(clk_bulk_prepare);





#endif /* CONFIG_HAVE_CLK_PREPARE */

#endif /* CONFIG_HAVE_CLK_PREPARE */

drivers/clk/rockchip/clk-rk3128.c

+7 −5
Original line number Original line Diff line number Diff line
@@ -315,13 +315,13 @@ static struct rockchip_clk_branch common_clk_branches[] __initdata = { 
			RK2928_CLKGATE_CON(10), 8, GFLAGS),

			RK2928_CLKGATE_CON(10), 8, GFLAGS),





	GATE(SCLK_PVTM_CORE, "clk_pvtm_core", "xin24m", 0,

	GATE(SCLK_PVTM_CORE, "clk_pvtm_core", "xin24m", 0,

			RK2928_CLKGATE_CON(10), 8, GFLAGS),

			RK2928_CLKGATE_CON(10), 0, GFLAGS),

	GATE(SCLK_PVTM_GPU, "clk_pvtm_gpu", "xin24m", 0,

	GATE(SCLK_PVTM_GPU, "clk_pvtm_gpu", "xin24m", 0,

			RK2928_CLKGATE_CON(10), 8, GFLAGS),

			RK2928_CLKGATE_CON(10), 1, GFLAGS),

	GATE(SCLK_PVTM_FUNC, "clk_pvtm_func", "xin24m", 0,

	GATE(SCLK_PVTM_FUNC, "clk_pvtm_func", "xin24m", 0,

			RK2928_CLKGATE_CON(10), 8, GFLAGS),

			RK2928_CLKGATE_CON(10), 2, GFLAGS),

	GATE(SCLK_MIPI_24M, "clk_mipi_24m", "xin24m", CLK_IGNORE_UNUSED,

	GATE(SCLK_MIPI_24M, "clk_mipi_24m", "xin24m", CLK_IGNORE_UNUSED,

			RK2928_CLKGATE_CON(10), 8, GFLAGS),

			RK2928_CLKGATE_CON(2), 15, GFLAGS),





	COMPOSITE(SCLK_SDMMC, "sclk_sdmmc0", mux_mmc_src_p, 0,

	COMPOSITE(SCLK_SDMMC, "sclk_sdmmc0", mux_mmc_src_p, 0,

			RK2928_CLKSEL_CON(11), 6, 2, MFLAGS, 0, 6, DFLAGS,

			RK2928_CLKSEL_CON(11), 6, 2, MFLAGS, 0, 6, DFLAGS,
@@ -541,7 +541,7 @@ static struct rockchip_clk_branch common_clk_branches[] __initdata = { 
	GATE(0, "pclk_grf", "pclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(5), 4, GFLAGS),

	GATE(0, "pclk_grf", "pclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(5), 4, GFLAGS),

	GATE(0, "pclk_mipiphy", "pclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(5), 0, GFLAGS),

	GATE(0, "pclk_mipiphy", "pclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(5), 0, GFLAGS),





	GATE(0, "pclk_pmu", "pclk_pmu_pre", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(9), 2, GFLAGS),

	GATE(0, "pclk_pmu", "pclk_pmu_pre", 0, RK2928_CLKGATE_CON(9), 2, GFLAGS),

	GATE(0, "pclk_pmu_niu", "pclk_pmu_pre", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(9), 3, GFLAGS),

	GATE(0, "pclk_pmu_niu", "pclk_pmu_pre", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(9), 3, GFLAGS),





	/* PD_MMC */

	/* PD_MMC */
@@ -577,6 +577,8 @@ static const char *const rk3128_critical_clocks[] __initconst = { 
	"aclk_peri",

	"aclk_peri",

	"hclk_peri",

	"hclk_peri",

	"pclk_peri",

	"pclk_peri",

	"pclk_pmu",

	"sclk_timer5",

};

};





static struct rockchip_clk_provider *__init rk3128_common_clk_init(struct device_node *np)

static struct rockchip_clk_provider *__init rk3128_common_clk_init(struct device_node *np)

drivers/clk/samsung/clk-exynos4.c

+15 −0
Original line number Original line Diff line number Diff line
@@ -294,6 +294,18 @@ static const struct samsung_clk_reg_dump src_mask_suspend_e4210[] = { 
#define PLL_ENABLED	(1 << 31)

#define PLL_ENABLED	(1 << 31)

#define PLL_LOCKED	(1 << 29)

#define PLL_LOCKED	(1 << 29)





static void exynos4_clk_enable_pll(u32 reg)

{

	u32 pll_con = readl(reg_base + reg);

	pll_con |= PLL_ENABLED;

	writel(pll_con, reg_base + reg);



	while (!(pll_con & PLL_LOCKED)) {

		cpu_relax();

		pll_con = readl(reg_base + reg);

	}

}



static void exynos4_clk_wait_for_pll(u32 reg)

static void exynos4_clk_wait_for_pll(u32 reg)

{

{

	u32 pll_con;

	u32 pll_con;
@@ -315,6 +327,9 @@ static int exynos4_clk_suspend(void) 
	samsung_clk_save(reg_base, exynos4_save_pll,

	samsung_clk_save(reg_base, exynos4_save_pll,

				ARRAY_SIZE(exynos4_clk_pll_regs));

				ARRAY_SIZE(exynos4_clk_pll_regs));





	exynos4_clk_enable_pll(EPLL_CON0);

	exynos4_clk_enable_pll(VPLL_CON0);



	if (exynos4_soc == EXYNOS4210) {

	if (exynos4_soc == EXYNOS4210) {

		samsung_clk_save(reg_base, exynos4_save_soc,

		samsung_clk_save(reg_base, exynos4_save_soc,

					ARRAY_SIZE(exynos4210_clk_save));

					ARRAY_SIZE(exynos4210_clk_save));

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