Revert "clk: bcm2835: remove pllb" (dbe01b44) · Commits · 戴 / test

This reverts commit . Since we will be expanding the firmware clock driver, we'll need to remove the quirks to deal with the PLLB. However, we still want to expose the clock tree properly, so having that clock in the MMIO driver will allow that. Acked-by:

Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Tested-by:

Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by:

Maxime Ripard <maxime@cerno.tech> Link: https://lore.kernel.org/r/5d26a4c58248f5be7760a7f2f720a1310baea5dd.1592210452.git-series.maxime@cerno.tech Signed-off-by:

Stephen Boyd <sboyd@kernel.org>

drivers/clk/bcm/clk-bcm2835.c

+26 −4

Original line number	Diff line number	Diff line
		@@ -1684,10 +1684,32 @@ static const struct bcm2835_clk_desc clk_desc_array[] = {
		.fixed_divider = 1,
		.flags = CLK_SET_RATE_PARENT),

		/*
		* PLLB is used for the ARM's clock. Controlled by firmware, see
		* clk-raspberrypi.c.
		*/
		/* PLLB is used for the ARM's clock. */
		[BCM2835_PLLB] = REGISTER_PLL(
		SOC_ALL,
		.name = "pllb",
		.cm_ctrl_reg = CM_PLLB,
		.a2w_ctrl_reg = A2W_PLLB_CTRL,
		.frac_reg = A2W_PLLB_FRAC,
		.ana_reg_base = A2W_PLLB_ANA0,
		.reference_enable_mask = A2W_XOSC_CTRL_PLLB_ENABLE,
		.lock_mask = CM_LOCK_FLOCKB,

		.ana = &bcm2835_ana_default,

		.min_rate = 600000000u,
		.max_rate = 3000000000u,
		.max_fb_rate = BCM2835_MAX_FB_RATE),
		[BCM2835_PLLB_ARM] = REGISTER_PLL_DIV(
		SOC_ALL,
		.name = "pllb_arm",
		.source_pll = "pllb",
		.cm_reg = CM_PLLB,
		.a2w_reg = A2W_PLLB_ARM,
		.load_mask = CM_PLLB_LOADARM,
		.hold_mask = CM_PLLB_HOLDARM,
		.fixed_divider = 1,
		.flags = CLK_SET_RATE_PARENT),

		/*
		* PLLC is the core PLL, used to drive the core VPU clock.

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