Commit dbdf20db authored by Bernd Schmidt's avatar Bernd Schmidt Committed by Bryan Wu
Browse files

Blackfin arch: Faster C implementation of no-MPU CPLB handler 



This is a mixture ofcMichael McTernan's patch and the existing cplb-mpu code.

We ditch the old cplb-nompu implementation, which is a good example of
why a good algorithm in a HLL is preferrable to a bad algorithm written in
assembly.  Rather than try to construct a table of all posible CPLBs and
search it, we just create a (smaller) table of memory regions and
their attributes.  Some of the data structures are now unified for both
the mpu and nompu cases.  A lot of needless complexity in cplbinit.c is
removed.

Further optimizations:
  * compile cplbmgr.c with a lot of -ffixed-reg options, and omit saving
    these registers on the stack when entering a CPLB exception.
  * lose cli/nop/nop/sti sequences for some workarounds - these don't
  * make
    sense in an exception context

Additional code unification should be possible after this.

[Mike Frysinger <vapier.adi@gmail.com>:
 - convert CPP if statements to C if statements
 - remove redundant statements
 - use a do...while loop rather than a for loop to get slightly better
   optimization and to avoid gcc "may be used uninitialized" warnings ...
   we know that the [id]cplb_nr_bounds variables will never be 0, so this
   is OK
 - the no-mpu code was the last user of MAX_MEM_SIZE and with that rewritten,
   we can punt it
 - add some BUG_ON() checks to make sure we dont overflow the small
   cplb_bounds array
 - add i/d cplb entries for the bootrom because there is functions/data in
   there we want to access
 - we do not need a NULL trailing entry as any time we access the bounds
   arrays, we use the nr_bounds variable
]

Signed-off-by: default avatarMichael McTernan <mmcternan@airvana.com>
Signed-off-by: default avatarMike Frysinger <vapier.adi@gmail.com>
Signed-off-by: default avatarBernd Schmidt <bernds_cb1@t-online.de>
Signed-off-by: default avatarBryan Wu <cooloney@kernel.org>
parent 6651ece9

arch/blackfin/Kconfig

+0 −8
Original line number Diff line number Diff line
@@ -524,14 +524,6 @@ config MEM_SDGCTL 
	default 0x0

endmenu



config MAX_MEM_SIZE

	int "Max SDRAM Memory Size in MBytes"

	depends on !MPU

	default 512

	help

	  This is the max memory size that the kernel will create CPLB

	  tables for.  Your system will not be able to handle any more.



#

# Max & Min Speeds for various Chips

#

arch/blackfin/include/asm/context.S

+39 −0
Original line number Diff line number Diff line
@@ -357,3 +357,42 @@ 
	SYSCFG = [sp++];

	csync;

.endm



.macro save_context_cplb

	[--sp] = (R7:0, P5:0);

	[--sp] = fp;



	[--sp] = a0.x;

	[--sp] = a0.w;

	[--sp] = a1.x;

	[--sp] = a1.w;



	[--sp] = LC0;

	[--sp] = LC1;

	[--sp] = LT0;

	[--sp] = LT1;

	[--sp] = LB0;

	[--sp] = LB1;



	[--sp] = RETS;

.endm



.macro restore_context_cplb

	RETS = [sp++];



	LB1 = [sp++];

	LB0 = [sp++];

	LT1 = [sp++];

	LT0 = [sp++];

	LC1 = [sp++];

	LC0 = [sp++];



	a1.w = [sp++];

	a1.x = [sp++];

	a0.w = [sp++];

	a0.x = [sp++];



	fp = [sp++];



	(R7:0, P5:0) = [SP++];

.endm

arch/blackfin/include/asm/cplb-mpu.h

deleted100644 → 0
+0 −62
Original line number Diff line number Diff line 
/*

 * File:         include/asm-blackfin/cplbinit.h

 * Based on:

 * Author:

 *

 * Created:

 * Description:

 *

 * Modified:

 *               Copyright 2004-2006 Analog Devices Inc.

 *

 * Bugs:         Enter bugs at http://blackfin.uclinux.org/

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License as published by

 * the Free Software Foundation; either version 2 of the License, or

 * (at your option) any later version.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 *

 * You should have received a copy of the GNU General Public License

 * along with this program; if not, see the file COPYING, or write

 * to the Free Software Foundation, Inc.,

 * 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA

 */

#ifndef __ASM_BFIN_CPLB_MPU_H

#define __ASM_BFIN_CPLB_MPU_H

#include <linux/threads.h>



struct cplb_entry {

	unsigned long data, addr;

};



struct mem_region {

	unsigned long start, end;

	unsigned long dcplb_data;

	unsigned long icplb_data;

};



extern struct cplb_entry dcplb_tbl[NR_CPUS][MAX_CPLBS];

extern struct cplb_entry icplb_tbl[NR_CPUS][MAX_CPLBS];

extern int first_switched_icplb;

extern int first_mask_dcplb;

extern int first_switched_dcplb;



extern int nr_dcplb_miss[], nr_icplb_miss[], nr_icplb_supv_miss[];

extern int nr_dcplb_prot[], nr_cplb_flush[];



extern int page_mask_order;

extern int page_mask_nelts;



extern unsigned long *current_rwx_mask[NR_CPUS];



extern void flush_switched_cplbs(unsigned int);

extern void set_mask_dcplbs(unsigned long *, unsigned int);



extern void __noreturn panic_cplb_error(int seqstat, struct pt_regs *);



#endif /* __ASM_BFIN_CPLB_MPU_H */

arch/blackfin/include/asm/cplb.h

+4 −0
Original line number Diff line number Diff line
@@ -116,4 +116,8 @@ 
#define CPLB_INOCACHE   	CPLB_USER_RD | CPLB_VALID

#define CPLB_IDOCACHE   	CPLB_INOCACHE | CPLB_L1_CHBL



#define FAULT_RW        (1 << 16)

#define FAULT_USERSUPV  (1 << 17)

#define FAULT_CPLBBITS  0x0000ffff



#endif				/* _CPLB_H */

arch/blackfin/include/asm/cplbinit.h

+34 −74
Original line number Diff line number Diff line
@@ -32,96 +32,56 @@ 


#include <asm/blackfin.h>

#include <asm/cplb.h>

#include <linux/threads.h>



#ifdef CONFIG_MPU



#include <asm/cplb-mpu.h>

extern void bfin_icache_init(struct cplb_entry *icplb_tbl);

extern void bfin_dcache_init(struct cplb_entry *icplb_tbl);



#ifdef CONFIG_CPLB_SWITCH_TAB_L1

# define PDT_ATTR __attribute__((l1_data))

#else

# define PDT_ATTR

#endif



#define INITIAL_T 0x1

#define SWITCH_T  0x2

#define I_CPLB    0x4

#define D_CPLB    0x8

struct cplb_entry {

	unsigned long data, addr;

};



#define ASYNC_MEMORY_CPLB_COVERAGE  ((ASYNC_BANK0_SIZE + ASYNC_BANK1_SIZE + \

				ASYNC_BANK2_SIZE + ASYNC_BANK3_SIZE) / SIZE_4M)

struct cplb_boundary {

	unsigned long eaddr; /* End of this region.  */

	unsigned long data; /* CPLB data value.  */

};



#define CPLB_MEM CONFIG_MAX_MEM_SIZE

extern struct cplb_boundary dcplb_bounds[];

extern struct cplb_boundary icplb_bounds[];

extern int dcplb_nr_bounds, icplb_nr_bounds;



/*

* Number of required data CPLB switchtable entries

* MEMSIZE / 4 (we mostly install 4M page size CPLBs

* approx 16 for smaller 1MB page size CPLBs for allignment purposes

* 1 for L1 Data Memory

* possibly 1 for L2 Data Memory

* 1 for CONFIG_DEBUG_HUNT_FOR_ZERO

* 1 for ASYNC Memory

*/

#define MAX_SWITCH_D_CPLBS (((CPLB_MEM / 4) + 16 + 1 + 1 + 1 \

				 + ASYNC_MEMORY_CPLB_COVERAGE) * 2)

extern struct cplb_entry dcplb_tbl[NR_CPUS][MAX_CPLBS];

extern struct cplb_entry icplb_tbl[NR_CPUS][MAX_CPLBS];

extern int first_switched_icplb;

extern int first_switched_dcplb;



/*

* Number of required instruction CPLB switchtable entries

* MEMSIZE / 4 (we mostly install 4M page size CPLBs

* approx 12 for smaller 1MB page size CPLBs for allignment purposes

* 1 for L1 Instruction Memory

* possibly 1 for L2 Instruction Memory

* 1 for CONFIG_DEBUG_HUNT_FOR_ZERO

*/

#define MAX_SWITCH_I_CPLBS (((CPLB_MEM / 4) + 12 + 1 + 1 + 1) * 2)

extern int nr_dcplb_miss[], nr_icplb_miss[], nr_icplb_supv_miss[];

extern int nr_dcplb_prot[], nr_cplb_flush[];



/* Number of CPLB table entries, used for cplb-nompu. */

#define CPLB_TBL_ENTRIES (16 * 4)

#ifdef CONFIG_MPU



enum {

	ZERO_P, L1I_MEM, L1D_MEM, L2_MEM, SDRAM_KERN, SDRAM_RAM_MTD, SDRAM_DMAZ,

	RES_MEM, ASYNC_MEM, OCB_ROM

};

extern int first_mask_dcplb;



struct cplb_desc {

	u32 start; /* start address */

	u32 end; /* end address */

	u32 psize; /* prefered size if any otherwise 1MB or 4MB*/

	u16 attr;/* attributes */

	u16 i_conf;/* I-CPLB DATA */

	u16 d_conf;/* D-CPLB DATA */

	u16 valid;/* valid */

	const s8 name[30];/* name */

};

extern int page_mask_order;

extern int page_mask_nelts;



struct cplb_tab {

  u_long *tab;

	u16 pos;

	u16 size;

};

extern unsigned long *current_rwx_mask[NR_CPUS];



extern u_long icplb_tables[NR_CPUS][CPLB_TBL_ENTRIES+1];

extern u_long dcplb_tables[NR_CPUS][CPLB_TBL_ENTRIES+1];

extern void flush_switched_cplbs(unsigned int);

extern void set_mask_dcplbs(unsigned long *, unsigned int);



/* Till here we are discussing about the static memory management model.

 * However, the operating envoronments commonly define more CPLB

 * descriptors to cover the entire addressable memory than will fit into

 * the available on-chip 16 CPLB MMRs. When this happens, the below table

 * will be used which will hold all the potentially required CPLB descriptors

 *

 * This is how Page descriptor Table is implemented in uClinux/Blackfin.

 */



extern u_long ipdt_tables[NR_CPUS][MAX_SWITCH_I_CPLBS+1];

extern u_long dpdt_tables[NR_CPUS][MAX_SWITCH_D_CPLBS+1];

#ifdef CONFIG_CPLB_INFO

extern u_long ipdt_swapcount_tables[NR_CPUS][MAX_SWITCH_I_CPLBS];

extern u_long dpdt_swapcount_tables[NR_CPUS][MAX_SWITCH_D_CPLBS];

#endif

extern void bfin_icache_init(u_long icplbs[]);

extern void bfin_dcache_init(u_long dcplbs[]);

extern void __noreturn panic_cplb_error(int seqstat, struct pt_regs *);



#endif /* CONFIG_MPU */



extern void bfin_icache_init(struct cplb_entry *icplb_tbl);

extern void bfin_dcache_init(struct cplb_entry *icplb_tbl);



#if defined(CONFIG_BFIN_DCACHE) || defined(CONFIG_BFIN_ICACHE)

extern void generate_cplb_tables_all(void);

extern void generate_cplb_tables_cpu(unsigned int cpu);

#endif

#endif

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