drm/i915: Convert some more bits to use engine mmio accessors (dbc65183) · Commits · 戴 / test

drivers/gpu/drm/i915/gt/intel_lrc.c

+13 −14

Original line number	Diff line number	Diff line
		@@ -2021,31 +2021,30 @@ static int intel_init_workaround_bb(struct intel_engine_cs *engine)

		static void enable_execlists(struct intel_engine_cs *engine)
		{
		struct drm_i915_private *dev_priv = engine->i915;

		intel_engine_set_hwsp_writemask(engine, ~0u); /* HWSTAM */

		if (INTEL_GEN(dev_priv) >= 11)
		I915_WRITE(RING_MODE_GEN7(engine),
		if (INTEL_GEN(engine->i915) >= 11)
		ENGINE_WRITE(engine,
		RING_MODE_GEN7,
		_MASKED_BIT_ENABLE(GEN11_GFX_DISABLE_LEGACY_MODE));
		else
		I915_WRITE(RING_MODE_GEN7(engine),
		ENGINE_WRITE(engine,
		RING_MODE_GEN7,
		_MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE));

		I915_WRITE(RING_MI_MODE(engine->mmio_base),
		_MASKED_BIT_DISABLE(STOP_RING));
		ENGINE_WRITE(engine, RING_MI_MODE, _MASKED_BIT_DISABLE(STOP_RING));

		I915_WRITE(RING_HWS_PGA(engine->mmio_base),
		ENGINE_WRITE(engine,
		RING_HWS_PGA,
		i915_ggtt_offset(engine->status_page.vma));
		POSTING_READ(RING_HWS_PGA(engine->mmio_base));
		ENGINE_POSTING_READ(engine, RING_HWS_PGA);
		}

		static bool unexpected_starting_state(struct intel_engine_cs *engine)
		{
		struct drm_i915_private *dev_priv = engine->i915;
		bool unexpected = false;

		if (I915_READ(RING_MI_MODE(engine->mmio_base)) & STOP_RING) {
		if (ENGINE_READ(engine, RING_MI_MODE) & STOP_RING) {
		DRM_DEBUG_DRIVER("STOP_RING still set in RING_MI_MODE\n");
		unexpected = true;
		}

+3 −2

Original line number	Diff line number	Diff line
		@@ -1713,7 +1713,8 @@ static void gen7_ppgtt_enable(struct drm_i915_private *dev_priv)

		for_each_engine(engine, dev_priv, id) {
		/* GFX_MODE is per-ring on gen7+ */
		I915_WRITE(RING_MODE_GEN7(engine),
		ENGINE_WRITE(engine,
		RING_MODE_GEN7,
		_MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
		}
		}

+1 −1

Original line number	Diff line number	Diff line
		@@ -1219,7 +1219,7 @@ static void error_record_engine_registers(struct i915_gpu_state *error,
		if (HAS_PPGTT(dev_priv)) {
		int i;

		ee->vm_info.gfx_mode = I915_READ(RING_MODE_GEN7(engine));
		ee->vm_info.gfx_mode = ENGINE_READ(engine, RING_MODE_GEN7);

		if (IS_GEN(dev_priv, 6)) {
		ee->vm_info.pp_dir_base =

+1 −1

Original line number	Diff line number	Diff line
		@@ -2698,7 +2698,7 @@ enum i915_power_well_id {

		#define GFX_MODE _MMIO(0x2520)
		#define GFX_MODE_GEN7 _MMIO(0x229c)
		#define RING_MODE_GEN7(engine) _MMIO((engine)->mmio_base + 0x29c)
		#define RING_MODE_GEN7(base) _MMIO((base) + 0x29c)
		#define GFX_RUN_LIST_ENABLE (1 << 15)
		#define GFX_INTERRUPT_STEERING (1 << 14)
		#define GFX_TLB_INVALIDATE_EXPLICIT (1 << 13)

+2 −2

Original line number	Diff line number	Diff line
		@@ -1306,7 +1306,7 @@ static void guc_interrupts_capture(struct drm_i915_private *dev_priv)
		*/
		irqs = _MASKED_BIT_ENABLE(GFX_INTERRUPT_STEERING);
		for_each_engine(engine, dev_priv, id)
		I915_WRITE(RING_MODE_GEN7(engine), irqs);
		ENGINE_WRITE(engine, RING_MODE_GEN7, irqs);

		/* route USER_INTERRUPT to Host, all others are sent to GuC. */
		irqs = GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT \|
		@@ -1353,7 +1353,7 @@ static void guc_interrupts_release(struct drm_i915_private *dev_priv)
		irqs = _MASKED_FIELD(GFX_FORWARD_VBLANK_MASK, GFX_FORWARD_VBLANK_NEVER);
		irqs \|= _MASKED_BIT_DISABLE(GFX_INTERRUPT_STEERING);
		for_each_engine(engine, dev_priv, id)
		I915_WRITE(RING_MODE_GEN7(engine), irqs);
		ENGINE_WRITE(engine, RING_MODE_GEN7, irqs);

		/* route all GT interrupts to the host */
		I915_WRITE(GUC_BCS_RCS_IER, 0);