Commit db9bde2f authored by Olof Johansson's avatar Olof Johansson
Browse files

Merge branch 'VExpress_DCSCB' of git://git.linaro.org/people/nico/linux into next/soc 



From Nicolas Pitre:

This is the first MCPM backend submission for VExpress running on RTSM
aka Fast Models implementing the big.LITTLE system architecture.  This
enables SMP secondary boot as well as CPU hotplug on this platform.

A big prerequisite for this support is the CCI driver from Lorenzo
included in this pull request.

Also included is Rob Herring's set_auxcr/get_auxcr allowing nicer code.

Signed-off-by: default avatarOlof Johansson <olof@lixom.net>

* 'VExpress_DCSCB' of git://git.linaro.org/people/nico/linux:
  ARM: vexpress: Select multi-cluster SMP operation if required
  ARM: vexpress/dcscb: handle platform coherency exit/setup and CCI
  ARM: vexpress/dcscb: do not hardcode number of CPUs per cluster
  ARM: vexpress/dcscb: add CPU use counts to the power up/down API implementation
  ARM: vexpress: introduce DCSCB support
  ARM: introduce common set_auxcr/get_auxcr functions
  drivers/bus: arm-cci: function to enable CCI ports from early boot code
  drivers: bus: add ARM CCI support
parents 6678e389 033a899c

Documentation/devicetree/bindings/arm/cci.txt

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=======================================================

ARM CCI cache coherent interconnect binding description

=======================================================



ARM multi-cluster systems maintain intra-cluster coherency through a

cache coherent interconnect (CCI) that is capable of monitoring bus

transactions and manage coherency, TLB invalidations and memory barriers.



It allows snooping and distributed virtual memory message broadcast across

clusters, through memory mapped interface, with a global control register

space and multiple sets of interface control registers, one per slave

interface.



Bindings for the CCI node follow the ePAPR standard, available from:



www.power.org/documentation/epapr-version-1-1/



with the addition of the bindings described in this document which are

specific to ARM.



* CCI interconnect node



	Description: Describes a CCI cache coherent Interconnect component



	Node name must be "cci".

	Node's parent must be the root node /, and the address space visible

	through the CCI interconnect is the same as the one seen from the

	root node (ie from CPUs perspective as per DT standard).

	Every CCI node has to define the following properties:



	- compatible

		Usage: required

		Value type: <string>

		Definition: must be set to

			    "arm,cci-400"



	- reg

		Usage: required

		Value type: <prop-encoded-array>

		Definition: A standard property. Specifies base physical

			    address of CCI control registers common to all

			    interfaces.



	- ranges:

		Usage: required

		Value type: <prop-encoded-array>

		Definition: A standard property. Follow rules in the ePAPR for

			    hierarchical bus addressing. CCI interfaces

			    addresses refer to the parent node addressing

			    scheme to declare their register bases.



	CCI interconnect node can define the following child nodes:



	- CCI control interface nodes



		Node name must be "slave-if".

		Parent node must be CCI interconnect node.



		A CCI control interface node must contain the following

		properties:



		- compatible

			Usage: required

			Value type: <string>

			Definition: must be set to

				    "arm,cci-400-ctrl-if"



		- interface-type:

			Usage: required

			Value type: <string>

			Definition: must be set to one of {"ace", "ace-lite"}

				    depending on the interface type the node

				    represents.



		- reg:

			Usage: required

			Value type: <prop-encoded-array>

			Definition: the base address and size of the

				    corresponding interface programming

				    registers.



* CCI interconnect bus masters



	Description: masters in the device tree connected to a CCI port

		     (inclusive of CPUs and their cpu nodes).



	A CCI interconnect bus master node must contain the following

	properties:



	- cci-control-port:

		Usage: required

		Value type: <phandle>

		Definition: a phandle containing the CCI control interface node

			    the master is connected to.



Example:



	cpus {

		#size-cells = <0>;

		#address-cells = <1>;



		CPU0: cpu@0 {

			device_type = "cpu";

			compatible = "arm,cortex-a15";

			cci-control-port = <&cci_control1>;

			reg = <0x0>;

		};



		CPU1: cpu@1 {

			device_type = "cpu";

			compatible = "arm,cortex-a15";

			cci-control-port = <&cci_control1>;

			reg = <0x1>;

		};



		CPU2: cpu@100 {

			device_type = "cpu";

			compatible = "arm,cortex-a7";

			cci-control-port = <&cci_control2>;

			reg = <0x100>;

		};



		CPU3: cpu@101 {

			device_type = "cpu";

			compatible = "arm,cortex-a7";

			cci-control-port = <&cci_control2>;

			reg = <0x101>;

		};



	};



	dma0: dma@3000000 {

		compatible = "arm,pl330", "arm,primecell";

		cci-control-port = <&cci_control0>;

		reg = <0x0 0x3000000 0x0 0x1000>;

		interrupts = <10>;

		#dma-cells = <1>;

		#dma-channels = <8>;

		#dma-requests = <32>;

	};



	cci@2c090000 {

		compatible = "arm,cci-400";

		#address-cells = <1>;

		#size-cells = <1>;

		reg = <0x0 0x2c090000 0 0x1000>;

		ranges = <0x0 0x0 0x2c090000 0x6000>;



		cci_control0: slave-if@1000 {

			compatible = "arm,cci-400-ctrl-if";

			interface-type = "ace-lite";

			reg = <0x1000 0x1000>;

		};



		cci_control1: slave-if@4000 {

			compatible = "arm,cci-400-ctrl-if";

			interface-type = "ace";

			reg = <0x4000 0x1000>;

		};



		cci_control2: slave-if@5000 {

			compatible = "arm,cci-400-ctrl-if";

			interface-type = "ace";

			reg = <0x5000 0x1000>;

		};

	};



This CCI node corresponds to a CCI component whose control registers sits

at address 0x000000002c090000.

CCI slave interface @0x000000002c091000 is connected to dma controller dma0.

CCI slave interface @0x000000002c094000 is connected to CPUs {CPU0, CPU1};

CCI slave interface @0x000000002c095000 is connected to CPUs {CPU2, CPU3};

Documentation/devicetree/bindings/arm/rtsm-dcscb.txt

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ARM Dual Cluster System Configuration Block

-------------------------------------------



The Dual Cluster System Configuration Block (DCSCB) provides basic

functionality for controlling clocks, resets and configuration pins in

the Dual Cluster System implemented by the Real-Time System Model (RTSM).



Required properties:



- compatible : should be "arm,rtsm,dcscb"



- reg : physical base address and the size of the registers window



Example:



	dcscb@60000000 {

		compatible = "arm,rtsm,dcscb";

		reg = <0x60000000 0x1000>;

	};

arch/arm/include/asm/cp15.h

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@@ -61,6 +61,20 @@ static inline void set_cr(unsigned int val) 
	isb();

}



static inline unsigned int get_auxcr(void)

{

	unsigned int val;

	asm("mrc p15, 0, %0, c1, c0, 1	@ get AUXCR" : "=r" (val));

	return val;

}



static inline void set_auxcr(unsigned int val)

{

	asm volatile("mcr p15, 0, %0, c1, c0, 1	@ set AUXCR"

	  : : "r" (val));

	isb();

}



#ifndef CONFIG_SMP

extern void adjust_cr(unsigned long mask, unsigned long set);

#endif

arch/arm/mach-vexpress/Kconfig

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@@ -57,4 +57,13 @@ config ARCH_VEXPRESS_CORTEX_A5_A9_ERRATA 
config ARCH_VEXPRESS_CA9X4

	bool "Versatile Express Cortex-A9x4 tile"



config ARCH_VEXPRESS_DCSCB

	bool "Dual Cluster System Control Block (DCSCB) support"

	depends on MCPM

	select ARM_CCI

	help

	  Support for the Dual Cluster System Configuration Block (DCSCB).

	  This is needed to provide CPU and cluster power management

	  on RTSM implementing big.LITTLE.



endmenu

arch/arm/mach-vexpress/Makefile

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@@ -6,5 +6,6 @@ ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include \ 


obj-y					:= v2m.o

obj-$(CONFIG_ARCH_VEXPRESS_CA9X4)	+= ct-ca9x4.o

obj-$(CONFIG_ARCH_VEXPRESS_DCSCB)	+= dcscb.o	dcscb_setup.o

obj-$(CONFIG_SMP)			+= platsmp.o

obj-$(CONFIG_HOTPLUG_CPU)		+= hotplug.o

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