Commit db91427b authored by Christoph Hellwig's avatar Christoph Hellwig
Browse files

MIPS: document mixing "slightly different CCAs" 



Based on an email from Paul Burton, quoting section 4.8 "Cacheability and
Coherency Attributes and Access Types" of "MIPS Architecture Volume 1:
Introduction to the MIPS32 Architecture" (MD00080, revision 6.01).

Signed-off-by: default avatarChristoph Hellwig <hch@lst.de>
Acked-by: default avatarPaul Burton <paul.burton@mips.com>
parent 3e4e1d3f

arch/mips/Kconfig

+7 −0
Original line number Original line Diff line number Diff line
@@ -1119,6 +1119,13 @@ config DMA_PERDEV_COHERENT 




config DMA_NONCOHERENT

config DMA_NONCOHERENT

	bool

	bool

	#

	# MIPS allows mixing "slightly different" Cacheability and Coherency

	# Attribute bits.  It is believed that the uncached access through

	# KSEG1 and the implementation specific "uncached accelerated" used

	# by pgprot_writcombine can be mixed, and the latter sometimes provides

	# significant advantages.

	#

	select ARCH_HAS_DMA_WRITE_COMBINE

	select ARCH_HAS_DMA_WRITE_COMBINE

	select ARCH_HAS_SYNC_DMA_FOR_DEVICE

	select ARCH_HAS_SYNC_DMA_FOR_DEVICE

	select ARCH_HAS_UNCACHED_SEGMENT

	select ARCH_HAS_UNCACHED_SEGMENT

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