Merge tag 'usb-5.7-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb

Contact:	Heikki Krogerus <heikki.krogerus@linux.intel.com>

Description:

		The supported power roles. This attribute can be used to request

		power role swap on the port when the port supports USB Power

		Delivery. Swapping is supported as synchronous operation, so

		write(2) to the attribute will not return until the operation

		has finished. The attribute is notified about role changes so

		that poll(2) on the attribute wakes up. Change on the role will

		also generate uevent KOBJ_CHANGE. The current role is show in

		brackets, for example "[source] sink" when in source mode.

		power role swap on the port. Swapping is supported as

		synchronous operation, so write(2) to the attribute will not

		return until the operation has finished. The attribute is

		notified about role changes so that poll(2) on the attribute

		wakes up. Change on the role will also generate uevent

		KOBJ_CHANGE. The current role is show in brackets, for example

		"[source] sink" when in source mode.

		Valid values: source, sink

Description:

		Revision number of the supported USB Type-C specification.

What:		/sys/class/typec/<port>/orientation

Date:		February 2020

Contact:	Badhri Jagan Sridharan <badhri@google.com>

Description:

		Indicates the active orientation of the Type-C connector.

		Valid values:

		- "normal": CC1 orientation

		- "reverse": CC2 orientation

		- "unknown": Orientation cannot be determined.

USB Type-C partner devices (eg. /sys/class/typec/port0-partner/)

  compatible:

    enum:

      - amlogic,meson-g12a-usb2-phy

      - amlogic,meson-a1-usb2-phy

  reg:

    maxItems: 1

  - reset-names

  - "#phy-cells"

if:

  properties:

    compatible:

      enum:

        - amlogic,meson-a1-usb-ctrl

then:

  properties:

    power-domains:

      maxItems: 1

  required:

    - power-domains

examples:

  - |

    phy@36000 {

Cadence MHDP DisplayPort SD0801 PHY binding

===========================================

This binding describes the Cadence SD0801 PHY hardware included with

the Cadence MHDP DisplayPort controller.

-------------------------------------------------------------------------------

Required properties (controller (parent) node):

- compatible	: Should be "cdns,dp-phy"

- reg		: Defines the following sets of registers in the parent

		  mhdp device:

			- Offset of the DPTX PHY configuration registers

			- Offset of the SD0801 PHY configuration registers

- #phy-cells	: from the generic PHY bindings, must be 0.

Optional properties:

- num_lanes	: Number of DisplayPort lanes to use (1, 2 or 4)

- max_bit_rate	: Maximum DisplayPort link bit rate to use, in Mbps (2160,

		  2430, 2700, 3240, 4320, 5400 or 8100)

-------------------------------------------------------------------------------

Example:

	dp_phy: phy@f0fb030a00 {

		compatible = "cdns,dp-phy";

		reg = <0xf0 0xfb030a00 0x0 0x00000040>,

		      <0xf0 0xfb500000 0x0 0x00100000>;

		num_lanes = <4>;

		max_bit_rate = <8100>;

		#phy-cells = <0>;

	};

# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)

%YAML 1.2

---

$id: "http://devicetree.org/schemas/phy/phy-cadence-torrent.yaml#"

$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: Cadence Torrent SD0801 PHY binding for DisplayPort

description:

  This binding describes the Cadence SD0801 PHY (also known as Torrent PHY)

  hardware included with the Cadence MHDP DisplayPort controller.

maintainers:

  - Swapnil Jakhade <sjakhade@cadence.com>

  - Yuti Amonkar <yamonkar@cadence.com>

properties:

  compatible:

    enum:

      - cdns,torrent-phy

      - ti,j721e-serdes-10g

  '#address-cells':

    const: 1

  '#size-cells':

    const: 0

  clocks:

    maxItems: 1

    description:

      PHY reference clock. Must contain an entry in clock-names.

  clock-names:

    const: refclk

  reg:

    minItems: 1

    maxItems: 2

    items:

      - description: Offset of the Torrent PHY configuration registers.

      - description: Offset of the DPTX PHY configuration registers.

  reg-names:

    minItems: 1

    maxItems: 2

    items:

      - const: torrent_phy

      - const: dptx_phy

  resets:

    maxItems: 1

    description:

      Torrent PHY reset.

      See Documentation/devicetree/bindings/reset/reset.txt

patternProperties:

  '^phy@[0-7]+$':

    type: object

    description:

      Each group of PHY lanes with a single master lane should be represented as a sub-node.

    properties:

      reg:

        description:

          The master lane number. This is the lowest numbered lane in the lane group.

      resets:

        minItems: 1

        maxItems: 4

        description:

          Contains list of resets, one per lane, to get all the link lanes out of reset.

      "#phy-cells":

        const: 0

      cdns,phy-type:

        description:

          Specifies the type of PHY for which the group of PHY lanes is used.

          Refer include/dt-bindings/phy/phy.h. Constants from the header should be used.

        allOf:

          - $ref: /schemas/types.yaml#/definitions/uint32

          - enum: [1, 2, 3, 4, 5, 6]

      cdns,num-lanes:

        description:

          Number of DisplayPort lanes.

        allOf:

          - $ref: /schemas/types.yaml#/definitions/uint32

          - enum: [1, 2, 4]

        default: 4

      cdns,max-bit-rate:

        description:

          Maximum DisplayPort link bit rate to use, in Mbps

        allOf:

          - $ref: /schemas/types.yaml#/definitions/uint32

          - enum: [2160, 2430, 2700, 3240, 4320, 5400, 8100]

        default: 8100

    required:

      - reg

      - resets

      - "#phy-cells"

      - cdns,phy-type

    additionalProperties: false

required:

  - compatible

  - "#address-cells"

  - "#size-cells"

  - clocks

  - clock-names

  - reg

  - reg-names

  - resets

additionalProperties: false

examples:

  - |

    #include <dt-bindings/phy/phy.h>

    torrent_phy: torrent-phy@f0fb500000 {

          compatible = "cdns,torrent-phy";

          reg = <0xf0 0xfb500000 0x0 0x00100000>,

                <0xf0 0xfb030a00 0x0 0x00000040>;

          reg-names = "torrent_phy", "dptx_phy";

          resets = <&phyrst 0>;

          clocks = <&ref_clk>;

          clock-names = "refclk";

          #address-cells = <1>;

          #size-cells = <0>;

          torrent_phy_dp: phy@0 {

                    reg = <0>;

                    resets = <&phyrst 1>, <&phyrst 2>,

                             <&phyrst 3>, <&phyrst 4>;

                    #phy-cells = <0>;

                    cdns,phy-type = <PHY_TYPE_DP>;

                    cdns,num-lanes = <4>;

                    cdns,max-bit-rate = <8100>;

          };

    };

...

		  "mediatek,mt8173-u3phy";

		  make use of "mediatek,generic-tphy-v1" on mt2701 instead and

		  "mediatek,generic-tphy-v2" on mt2712 instead.

 - clocks	: (deprecated, use port's clocks instead) a list of phandle +

		  clock-specifier pairs, one for each entry in clock-names

 - clock-names	: (deprecated, use port's one instead) must contain

		  "u3phya_ref": for reference clock of usb3.0 analog phy.

- #address-cells:	the number of cells used to represent physical

		base addresses.

- #size-cells:	the number of cells used to represent the size of an address.

- ranges:	the address mapping relationship to the parent, defined with

		- empty value: if optional 'reg' is used.

		- non-empty value: if optional 'reg' is not used. should set

			the child's base address to 0, the physical address

			within parent's address space, and the length of

			the address map.

Required nodes	: a sub-node is required for each port the controller

		  provides. Address range information including the usual

Required properties (port (child) node):

- reg		: address and length of the register set for the port.

- clocks	: a list of phandle + clock-specifier pairs, one for each

		  entry in clock-names

- clock-names	: must contain

		  "ref": 48M reference clock for HighSpeed analog phy; and 26M

			reference clock for SuperSpeed analog phy, sometimes is

			24M, 25M or 27M, depended on platform.

- #phy-cells	: should be 1 (See second example)

		  cell after port phandle is phy type from:

			- PHY_TYPE_USB2

			- PHY_TYPE_SATA

Optional properties (PHY_TYPE_USB2 port (child) node):

- clocks	: a list of phandle + clock-specifier pairs, one for each

		  entry in clock-names

- clock-names	: may contain

		  "ref": 48M reference clock for HighSpeed (digital) phy; and 26M

			reference clock for SuperSpeed (digital) phy, sometimes is

			24M, 25M or 27M, depended on platform.

		  "da_ref": the reference clock of analog phy, used if the clocks

			of analog and digital phys are separated, otherwise uses

			"ref" clock only if needed.

- mediatek,eye-src	: u32, the value of slew rate calibrate

- mediatek,eye-vrt	: u32, the selection of VRT reference voltage

- mediatek,eye-term	: u32, the selection of HS_TX TERM reference voltage

- mediatek,bc12	: bool, enable BC12 of u2phy if support it

- mediatek,discth	: u32, the selection of disconnect threshold

- mediatek,intr	: u32, the selection of internal R (resistance)

Example: