Commit db31af12 authored Jun 03, 2019 by Jun Lei Committed by Alex Deucher Jul 18, 2019

drm/amd/display: cap DCFCLK hardmin to 507 for NV10



[why]
Due to limitation in SMU/PPLIB, it is not possible to know Fmax @ Vmin for DCFCLK.
This causes issues at high display configurations where extra headroom of DCFCLK
can enable P-state switching

[how]
Use existing override logic.  If override not defined, then force
min = 507

Signed-off-by: Jun Lei <Jun.Lei@amd.com>
Reviewed-by: Eric Yang <eric.yang2@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

parent 5d109be3

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c

+4 −0

Original line number	Diff line number	Diff line
		@@ -2643,6 +2643,10 @@ static void update_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_

		if (dc->bb_overrides.min_dcfclk_mhz > 0)
		min_dcfclk = dc->bb_overrides.min_dcfclk_mhz;
		else
		// Accounting for SOC/DCF relationship, we can go as high as
		// 506Mhz in Vmin. We need to code 507 since SMU will round down to 506.
		min_dcfclk = 507;

		for (i = 0; i < num_states; i++) {
		int min_fclk_required_by_uclk;

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