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Currently syscon has a fixed configuration of 32 bits for register and values widths. In some cases, it would be desirable to be able to customize the value width. For example, certain boards (like the ones manufactured by Technologic Systems) have a FPGA that is memory-mapped, but its registers are only 16-bit wide. This patch adds an optional "reg-io-width" DT binding for syscon that allows to change the width for the data bus (i.e. val_bits). If this property is provided, it will also set the register stride to reg-io-width's value. If not provided, the default configuration is used. Signed-off-by:Damien Riegel <damien.riegel@savoirfairelinux.com> Acked-by:
Rob Herring <robh@kernel.org> Acked-by:
Arnd Bergmann <arnd@arndb.de> Signed-off-by:
Lee Jones <lee.jones@linaro.org>
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