spi: Qualcomm Quad SPI(QSPI) documentation

Qualcomm Quad Serial Peripheral Interface (QSPI)

The QSPI controller allows SPI protocol communication in single, dual, or quad

wire transmission modes for read/write access to slaves such as NOR flash.

Required properties:

- compatible:	An SoC specific identifier followed by "qcom,qspi-v1", such as

		"qcom,sdm845-qspi", "qcom,qspi-v1"

- reg:		Should contain the base register location and length.

- interrupts:	Interrupt number used by the controller.

- clocks:	Should contain the core and AHB clock.

- clock-names:	Should be "core" for core clock and "iface" for AHB clock.

SPI slave nodes must be children of the SPI master node and can contain

properties described in Documentation/devicetree/bindings/spi/spi-bus.txt

Example:

	qspi: spi@88df000 {

		compatible = "qcom,sdm845-qspi", "qcom,qspi-v1";

		reg = <0x88df000 0x600>;

		#address-cells = <1>;

		#size-cells = <0>;

		interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;

		clock-names = "iface", "core";

		clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>,

			 <&gcc GCC_QSPI_CORE_CLK>;

		flash@0 {

			compatible = "jedec,spi-nor";

			reg = <0>;

			spi-max-frequency = <25000000>;

			spi-tx-bus-width = <2>;

			spi-rx-bus-width = <2>;

		};

	};