clk: stm32f4: fix: exclude values 0 and 1 for PLLQ (daffad21) · Commits · 戴 / test

0000: PLLQ = 0, wrong configuration 0001: PLLQ = 1, wrong configuration ... 0010: PLLQ = 2 0011: PLLQ = 3 0100: PLLQ = 4 ... 1111: PLLQ = 1 Use divider table to exclude 0 and 1 values. Fixes: ("clk: stm32f4: Add PLL_I2S & PLL_SAI for STM32F429/469 boards") Signed-off-by:

Gabriel Fernandez <gabriel.fernandez@st.com> Signed-off-by:

Stephen Boyd <sboyd@codeaurora.org>

drivers/clk/clk-stm32f4.c

+10 −3

Original line number	Diff line number	Diff line
		@@ -429,6 +429,13 @@ static const struct clk_div_table pll_divp_table[] = {
		{ 0, 2 }, { 1, 4 }, { 2, 6 }, { 3, 8 }, { 0 }
		};

		static const struct clk_div_table pll_divq_table[] = {
		{ 2, 2 }, { 3, 3 }, { 4, 4 }, { 5, 5 }, { 6, 6 }, { 7, 7 },
		{ 8, 8 }, { 9, 9 }, { 10, 10 }, { 11, 11 }, { 12, 12 }, { 13, 13 },
		{ 14, 14 }, { 15, 15 },
		{ 0 }
		};

		static const struct clk_div_table pll_divr_table[] = {
		{ 2, 2 }, { 3, 3 }, { 4, 4 }, { 5, 5 }, { 6, 6 }, { 7, 7 }, { 0 }
		};
		@@ -497,7 +504,7 @@ struct stm32f4_div_data {
		#define MAX_PLL_DIV 3
		static const struct stm32f4_div_data div_data[MAX_PLL_DIV] = {
		{ 16, 2, 0, pll_divp_table },
		{ 24, 4, CLK_DIVIDER_ONE_BASED, NULL },
		{ 24, 4, 0, pll_divq_table },
		{ 28, 3, 0, pll_divr_table },
		};

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