Commit dae0b74e authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'armsoc-fixes-nc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc 

Pull ARM SoC non-urgent fixes from Arnd Bergmann:
 "As usual, we queue up a few fixes that don't seem urgent enough to go
  in through -rc.

   - a number of randconfig warning fixes from Arnd
   - various small fixes for OMAP
   - one somewhat larger patch to restore the OMAP3 cpuidle tuning that
     was lost in a cleanup
   - a small regression fix for cns3xxx PCI"

* tag 'armsoc-fixes-nc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (26 commits)
  CNS3xxx: Fix PCI cns3xxx_write_config()
  MAINTAINERS: unify email addrs for Kevin Hilman
  CNS3xxx: remove unused *_VIRT definitions
  ARM: OMAP2+: Fix hwmod clock for l4_ls
  soc: TI knav_qmss: fix dma_addr_t printing
  ARM: prima2: always enable reset controller
  ARM: socfpga: hide unused functions
  ARM: ux500: fix ureachable iounmap()
  ARM: ks8695: fix __initdata annotation
  ARM: mvebu: mark mvebu_hwcc_pci_nb as __maybe_unused
  ARM: mv78xx0: avoid unused function warning
  ARM: orion: only select I2C_BOARDINFO when using I2C
  ARM: OMAP2+: Fix out of range register access with syscon_config.max_register
  ARM: OMAP3: Add cpuidle parameters table for omap3430
  ARM: davinci: make I2C support optional
  ARM: davinci: DA8xx+DMx combined kernels need PATCH_PHYS_VIRT
  ARM: davinci: avoid unused mityomapl138_pn_info variable
  ARM: davinci: limit DT support to DA850
  ARM: DRA7: hwmod: Add reset data for PCIe
  ARM: DRA7: hwmod: Fix OCP2SCP sysconfig
  ...
parents 142b9e6c 88e9da9a

MAINTAINERS

+3 −3
Original line number Diff line number Diff line
@@ -7887,7 +7887,7 @@ S: Maintained 
F:	arch/arm/*omap*/*clock*



OMAP POWER MANAGEMENT SUPPORT

M:	Kevin Hilman <khilman@deeprootsystems.com>

M:	Kevin Hilman <khilman@kernel.org>

L:	linux-omap@vger.kernel.org

S:	Maintained

F:	arch/arm/*omap*/*pm*
@@ -7991,7 +7991,7 @@ F: arch/arm/*omap*/usb* 
OMAP GPIO DRIVER

M:	Grygorii Strashko <grygorii.strashko@ti.com>

M:	Santosh Shilimkar <ssantosh@kernel.org>

M:	Kevin Hilman <khilman@deeprootsystems.com>

M:	Kevin Hilman <khilman@kernel.org>

L:	linux-omap@vger.kernel.org

S:	Maintained

F:	Documentation/devicetree/bindings/gpio/gpio-omap.txt
@@ -10048,7 +10048,7 @@ F: arch/arm/mach-s3c24xx/bast-irq.c 


TI DAVINCI MACHINE SUPPORT

M:	Sekhar Nori <nsekhar@ti.com>

M:	Kevin Hilman <khilman@deeprootsystems.com>

M:	Kevin Hilman <khilman@kernel.org>

T:	git git://gitorious.org/linux-davinci/linux-davinci.git

Q:	http://patchwork.kernel.org/project/linux-davinci/list/

S:	Supported

arch/arm/Kconfig

+1 −0
Original line number Diff line number Diff line
@@ -622,6 +622,7 @@ config ARCH_DAVINCI 
	select ARCH_HAS_HOLES_MEMORYMODEL

	select ARCH_REQUIRE_GPIOLIB

	select CLKDEV_LOOKUP

	select CPU_ARM926T

	select GENERIC_ALLOCATOR

	select GENERIC_CLOCKEVENTS

	select GENERIC_IRQ_CHIP

arch/arm/configs/mini2440_defconfig

+1 −0
Original line number Diff line number Diff line
@@ -158,6 +158,7 @@ CONFIG_I2C=y 
CONFIG_I2C_CHARDEV=y

CONFIG_I2C_S3C2410=y

CONFIG_I2C_SIMTEC=y

CONFIG_EEPROM_AT24=y

CONFIG_SPI=y

CONFIG_SPI_S3C24XX=y

CONFIG_SPI_SPIDEV=y

arch/arm/configs/s3c2410_defconfig

+1 −0
Original line number Diff line number Diff line
@@ -290,6 +290,7 @@ CONFIG_HW_RANDOM=y 
CONFIG_I2C_CHARDEV=m

CONFIG_I2C_S3C2410=y

CONFIG_I2C_SIMTEC=y

CONFIG_EEPROM_AT24=y

CONFIG_SPI=y

CONFIG_SPI_GPIO=m

CONFIG_SPI_S3C24XX=m

arch/arm/mach-cns3xxx/cns3xxx.h

+0 −6
Original line number Diff line number Diff line
@@ -162,13 +162,11 @@ 
#define CNS3XXX_L2C_BASE			0x92000000	/* L2 Cache Control */



#define CNS3XXX_PCIE0_MEM_BASE			0xA0000000	/* PCIe Port 0 IO/Memory Space */

#define CNS3XXX_PCIE0_MEM_BASE_VIRT		0xE0000000



#define CNS3XXX_PCIE0_HOST_BASE			0xAB000000	/* PCIe Port 0 RC Base */

#define CNS3XXX_PCIE0_HOST_BASE_VIRT		0xE1000000



#define CNS3XXX_PCIE0_IO_BASE			0xAC000000	/* PCIe Port 0 */

#define CNS3XXX_PCIE0_IO_BASE_VIRT		0xE2000000



#define CNS3XXX_PCIE0_CFG0_BASE			0xAD000000	/* PCIe Port 0 CFG Type 0 */

#define CNS3XXX_PCIE0_CFG0_BASE_VIRT		0xE3000000
@@ -177,16 +175,13 @@ 
#define CNS3XXX_PCIE0_CFG1_BASE_VIRT		0xE4000000



#define CNS3XXX_PCIE0_MSG_BASE			0xAF000000	/* PCIe Port 0 Message Space */

#define CNS3XXX_PCIE0_MSG_BASE_VIRT		0xE5000000



#define CNS3XXX_PCIE1_MEM_BASE			0xB0000000	/* PCIe Port 1 IO/Memory Space */

#define CNS3XXX_PCIE1_MEM_BASE_VIRT		0xE8000000



#define CNS3XXX_PCIE1_HOST_BASE			0xBB000000	/* PCIe Port 1 RC Base */

#define CNS3XXX_PCIE1_HOST_BASE_VIRT		0xE9000000



#define CNS3XXX_PCIE1_IO_BASE			0xBC000000	/* PCIe Port 1 */

#define CNS3XXX_PCIE1_IO_BASE_VIRT		0xEA000000



#define CNS3XXX_PCIE1_CFG0_BASE			0xBD000000	/* PCIe Port 1 CFG Type 0 */

#define CNS3XXX_PCIE1_CFG0_BASE_VIRT		0xEB000000
@@ -195,7 +190,6 @@ 
#define CNS3XXX_PCIE1_CFG1_BASE_VIRT		0xEC000000



#define CNS3XXX_PCIE1_MSG_BASE			0xBF000000	/* PCIe Port 1 Message Space */

#define CNS3XXX_PCIE1_MSG_BASE_VIRT		0xED000000



/*

 * Testchip peripheral and fpga gic regions

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