Commit da5d2ca8 authored by Mika Kuoppala's avatar Mika Kuoppala Committed by Chris Wilson
Browse files

drm/i915/icl: Wa_1607087056 



Avoid possible hang in tsg,vfe units by keeping
l3 clocks runnings.

Signed-off-by: default avatarMika Kuoppala <mika.kuoppala@linux.intel.com>
Reviewed-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20191015154411.9984-1-mika.kuoppala@linux.intel.com
parent 19306502

drivers/gpu/drm/i915/gt/intel_workarounds.c

+5 −0
Original line number Original line Diff line number Diff line
@@ -892,6 +892,11 @@ icl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal) 
	wa_write_or(wal,

	wa_write_or(wal,

		    GAMT_CHKN_BIT_REG,

		    GAMT_CHKN_BIT_REG,

		    GAMT_CHKN_DISABLE_L3_COH_PIPE);

		    GAMT_CHKN_DISABLE_L3_COH_PIPE);



	/* Wa_1607087056:icl */

	wa_write_or(wal,

		    SLICE_UNIT_LEVEL_CLKGATE,

		    L3_CLKGATE_DIS | L3_CR2X_CLKGATE_DIS);

}

}





static void

static void

drivers/gpu/drm/i915/i915_reg.h

+2 −0
Original line number Original line Diff line number Diff line
@@ -4050,6 +4050,8 @@ enum { 
#define  SARBUNIT_CLKGATE_DIS		(1 << 5)

#define  SARBUNIT_CLKGATE_DIS		(1 << 5)

#define  RCCUNIT_CLKGATE_DIS		(1 << 7)

#define  RCCUNIT_CLKGATE_DIS		(1 << 7)

#define  MSCUNIT_CLKGATE_DIS		(1 << 10)

#define  MSCUNIT_CLKGATE_DIS		(1 << 10)

#define  L3_CLKGATE_DIS			REG_BIT(16)

#define  L3_CR2X_CLKGATE_DIS		REG_BIT(17)





#define SUBSLICE_UNIT_LEVEL_CLKGATE	_MMIO(0x9524)

#define SUBSLICE_UNIT_LEVEL_CLKGATE	_MMIO(0x9524)

#define  GWUNIT_CLKGATE_DIS		(1 << 16)

#define  GWUNIT_CLKGATE_DIS		(1 << 16)

CRA Git | Maintained and supported by SUSTech CRA and CCSE